The analysis and location of timing errors in sequential logic circuits goes beyond merely triggering on a timing anomaly. Statistical analysis helps the designer understand the nature and cause of the problem. A parameter track function provides a fast way to locate timing errors in long data records.

Triggering a scope on a single anomaly, such as a setup time violation, can be helpful in studying individual timing events. A setup time sensitive trigger is shown in figure 1. A more complete picture of a timing problem is obtained by using histogramming. In figure 2 the Setup parameter is histogrammed (Trace F2) to see timing errors in more than 2,000,000 clock cycles. The histogram is displayed with expanded (zoomed) vertical scaling. Errors, indicated by the smaller distribution, occur at a rate of about 1 in 2000 clock cycles.

Figure 1:

Setup/hold trigger setup using SMART TRIGGER. The time between the data and clock transitions is measured using a logic pattern width trigger.

Figure 2:

The vertically zoomed histogram of Setup time shows distribution of minimum setup time of approximately

Trace F1 is a track of the same parameter. It shows the cycle to cycle variation in setup time over the 2,000 clock cycles represented in each acquisition. Note that there are 2 sets of narrow pulses which mark the location of the timing anomalies. The track function is time correlated with the source waveform. In figure 3 the areas of the acquired waveforms, traces 2 and 3, corresponding to the locations indicated by the track function are expanded horizontally using zoom displays. It is easy to see the pulse pair, located at the center of the trace, with a setup time of 567 ps.

Figure 3:

The track of Setup time

Note that the timing measurement parameters, such as setup time have a timing resolution of 1ps. This means that histogram and track based analysis provides usable timing information even for the fastest logic families. They are not limited by the minimum timing resolution of the trigger circuits.

In the final example, shown in figure 4, pass fail testing is used to automatically acquire individual timing errors. Testing is based on setup times which are smaller than 800 ps. This particular test has been set to stop the acquisition on failure. It could also have easily been setup to store the waveform or to provide a hard copy of the error using an optional high speed internal printer.

Figure 4:

Using Pass/Fail testing based on the setup time parameter to capture individual setup time violations

LeCroy Oscilloscopes provide users with multiple tools that allow detailed analysis of billions of timing events with resolutions down to picoseconds. In this example four different techniques have been shown including triggering on a setup time violation, histogramming setup time, tracking parameter values and locating violations, and using Pass/Fail testing to capture individual setup time anomalies. Any or all of these techniques can be used to validate and troubleshoot your design.