GENERAL2323A4222
PackagingDouble-width CAMACSingle-width CAMAC
START Input-3 V to +3 V-1.5 V to +1.5 V
STOP InputNIMNIM (Clear Input)
GATE WIDTH
Range100 nsec to 10 sec or Latch Mode170 nsec to 16.777215 msec
Jitter< 0.3% of setting150 psec R.M.S. max.
Accuracy0.2% of full scale200 psec time base error
Resolution0.1% of full scale1 nsec
Input to Output Delay24 nsec170 nsec typical
DELAYED OUT
Width10, 30, 100 or 300 nsecLatched until reset by CLEAR or next trigger if retrigger mode is selected
Occurs Trailing edge of gate pulseAt end of delay
Rise Time2 nsec max1 nsec
SignalNIM (-16 mA)OUT: Standard negative NIM at end of delay. OUT*: Complement of OUT.
Miscellaneous Delay setting programmable from 170 nsec to 16.777215 msec
ADDITIONAL INPUTS AND OUTPUTS
Delayed Pulse TTL/ECLP1 - P4. Each Channel PULSE OUT delivers a 1 nsec rise time 5 V pulse (into 50 W) when the corresponding time delay has elapsed; pulse width 150 nsec 10%.
BUSY NIM BUSY output state goes true in response to a valid Trigger and remains true until the end of the shortest delay or the end of the longest delay as seen by an internal switch.
ORNIM OR'd with gate
BLANKNIM vetos gate
POWER
24 V+50 mA/-75 mA+40 mA/-130 mA
12 V
6 V+1.8 A/-1.3 A+1.3 A/-2.5 A
21.6 W26.9 W
*Taken from +12 V if +6 V unavailable.