2367 FASTCAMAC Compatible Universal Logic Module
The CAMAC Model 2367 is a versatile general purpose programmable logic module employing a Xilinx 4013E Field Programmable Gate Array (FPGA), Texas Instruments TMS320F206S Digital Signal Processer (DSP), and 3 MByte RAM. With the 2367, CAMAC users have the ablility to solve a wide variety of Logic/Processing problems, all with a single module. It contains 59 front panel I/O lines, programmable as inputs or outputs, that are mapped to the user-programmable Xilinx FPGA, as well as three on board clocks at the user's disposal.
In addition to the ability to perform simple logic functions as well as elaborate arithmetic calculations, the RAM, FPGA, and DSP give the user the power to operate the 2367 in ways unavailable to the 2366 logic Module, e.g. as a histogramming memory module. The module also contains 64 kBytes of non-volatile memory internal to the DSP chip (principally for DSP program storage) and an on-board 64 kBytes of non-volatile EEPROM memory for FPGA program retention. Virtually no digital application is out of its range.
The desired logic operations are programmed in a Xilinx 4013E gate array chip. Any logic that can be implemented as a synchronous (clocked) state machine may be programmed, subject only to the size limitation of the Xilinx gate array of approximately 13,000 equivalent gates. There are 3 clocks available on-board (40, 20, and 10 MHz), and any of 3 special front panel inputs may also be used as clocks. Input and output signals use standard 10124 and 10125 TTL-ECL level translators. Input signals as short as 5 nanoseconds can be latched and synchronized with the internal state machine logic.
The FPGA can receive its configuration from either the EEPROM, or via a Xilinx .bit file uploaded via CAMAC commands. The EEPROM can hold two separate programs, and may be reprogrammed at any time, allowing the user to upload their own custom application. The FPGA is will automatically receive its configuration from the EEPROM upon power-up.
The 2367 is shipped with a EEPROM that holds the following configurations:
CAMAC Dataway & Memory Tester
With this configuration, the 2367 behaves as a CAMAC Dataway tester, and as million word memory. The DSP execution of a user program loaded in RAM can be started and stopped. This configuration is available on power-up, as long as the EEPROM is not overwritten.
FERA List Memory
With this configuration, the 2367 behaves similar to a LeCroy Model 4302 FERA Memory, with a depth of 512k addresses X 16 bit. The front panel is designed to receive the FERA WRITE STOBE and to return an ACKNOWLEDGE signal. Overflow and Full outputs are also available.
FASTCAMAC Model 2367 Functional Diagram
Mechanical: Single width standard CAMAC module
Power Requirements: +6 V at 1.8 A; -6V at 2.5 A
LEDs: 1 to indicate N line activity; 2 programmable via Xilinx Configuration
I/O lines: 59 differential ECL, configurable as inputs or outputs in groups of 4. Inputs are terminated with 112 ohms, outputs will drive 100 ohm lines.
Size: 3 Mbytes RAM:,
Configurations: 3M addresses x 8bit, 1.5M addresses x 16 bit, 1M addresses x 24 bit, 512k addresses x 48 bit
Accessible to DSP: 384 K bytes (one eighth of the total memory), single cycle execution at 100ns per cycle.
Accessible to FPGA: Entire RAM is accessible.
40 MHz, 20 MHz, and 10 MHz clocks from a crystal oscillator on-board. Clock precision 0.1%.
I/O: All front panel I/O lines to and from the Xilinx chip ???
Xilinx Configurability Options:
1. Default: FPGA configured by on-board EEPROM (Bank 0) on power up
2. Reload: Can reload program from EEPROM bank 0 or 1 via CAMAC commands
3. Configurable via CAMAC: At any time, independently of EEPROM. Xilinx software is required to generate the configuration file. The Xilinx ".bit" file format or ".mcs" file formats contains the configuration information. (Software for upload the "bit" file format the 2367 is included)
CAMAC Interface: Programming, 8 bit write only interface. Test for successful programming. After configuration, all CAMAC control and data lines (N, F, A, 24R/W, C, Z, S1, S2, Q, X, L) are available to the Xilinx chip. Only 1 function code (F30) is reserved for re-entering program mode, all others being available for user functions.
Configurations: Can hold 2 FPGA configurations (Bank 0 and Bank
Reprogrammability: EEPROM may be reprogrammed via CAMAC commands at any time.
Program Retention: EEPROM retains FPGA configutations without power for .....
General: (Please see the data sheet from TI for detailed information on using the TMS320F206S)
Copyrightę February 1998.. LeCroy is a registered trademark of LeCroy Corporation. All
rights reserved. Information in this publication supersedes all earlier versions.
Specifications and prices subject to change without notice.