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2373 16 x 16 MEMORY LOOKUP UNIT
- High Performance Programmable Logic
- Fast Decisions at up to 20 MHz, Pipelined Architecture
- ECLine Compatible for Versatile and Economical Interconnections
- Exceeds Any Other Method Used for Fast, Intelligent, In-Crate, Programmable
Deci sion Logic and Computation
- Compatible with ECLine First Level Trigger Modules, Discriminators,
ADC/TDC, and MWPC Systems
SOPHISTICATED PATTERN RECOGNITION AND TRIGGER DECISIONS
LeCroy trigger processor modules place extraordinary computational power
and speed in the data acquisition crate. These modules are fully compatible
with the ECLine standard for data transmission at 10MHz speeds using economical
ribbon cable interconnections. Their varied functions are programmable by
computer as re quired by the user. A single module can replace crates of
conventional logic modules, and yet perform the tasks better, faster, and
with greater reliability.
LeCroy trigger processor data handler modules are designed to meet the needs
of experiments that have become more complex and the increased demands on
data acquisition performance. Raw data can be quickly analyzed, sorted,
manipulated and stored before entering any microprocessing system or host
computer. The speeds achieved by this method exceed those of local microprocessor
systems. By being able to quickly analyze incom ing data, a decision to
take (valuable) time to record the data can be made intelligently.
The LeCroy line of trigger processor modules consists of units which have
separate discrete functions and operations. These independent modules can
be combined to make a high performance system configured to the requirements
of the specific experiment.
The Model 2373 Memory Lookup Unit (MLU) can perform functions similar to
the ALU but it is not restricted to arithmetic or logical operations. In
the MLU the input word is a RAM address and the output is the contents of
the input word address. The user pre-programs responses to all combinations
of input words. This unit provides 20MHz rates for up to 16 bits input.
Intermediate data storage can be accommodated by either a simple memory
module or by a specialized unit.
The Model 2371 Data Register permits storing a particular word on a databus
for use at a later time. For example, the latched data might be the identification
label of the module putting data out onto the bus.
Trigger processing modules provide a range of capability at exceptional
speeds. Fast, intelligent data pre-pro cessing, analyzing, calibrating,
error checking, track-finding, event counting, etc., can significantly improve
the efficiency of data acquisition, and can provide pre-processed results
before the data leaves the local crate. They put the processing power where
it is needed and in the way it can be used.
Model 2371- Data Register
The Data Register accepts and then distributes one word of data on the ECL
bus. It accepts a 16-bit ECL input word when the unit's STROBE and ENABLE
signals are present. The input word is then transferred to two output words,
in parallel, and a data ready strobe is issued.
As an example, an MLU might be used to calibrate a group of FERAs, which
put their data out on an ECL bus. The first word from each FERA is an ID
number together with a bit that identifies it as the ID number. This extra
bit can be used to strobe the Data Register whose input is from the ECL
bus coming from the FERAs. Then the output of the Data Register can be hard-wired
with the ECL bus so that the subsequent words from the FERAs (which are
digitized data) are then combined with the address given at the beginning
of each FERA's readout cycle. The MLU can then be presented with a data
word which has the FERA ID number in the uppermost bits and the data words
in the lower bits.
Model 2373- Memory Lookup Unit
The Model 2373, an improved version of the LeCroy Model 2372 Memory Lookup
Module (MLU), allows a 16-bit input address word to generate a 16-bit
output word. The short cycle time of the 2373 makes it very desir able
for complex functions required of trigger logic or high speed data processing.
In normal use, the MLU is first downloaded via CAMAC with the required data
and then verified via CAMAC. The stored information, which defines the function
of the MLU, is accessed via the 16-bit front panel Data-In and Data -Out
connectors for real time applications. In this way, high speed mapping of
16-bit input words into 16-bit output words is accomplished at data rates
as high as 22 MHz.
The function of the MLU is user defined to meet the application. Virtually
any function may be defined: angle logic or clusterized track multiplicity
are examples of complex trigger functions. When used as a trigger processor
element, the MLU may be used for any operation which is a one-to-one mapping.
In conjunction with an ADC, the MLU can be loaded with the calibration to
energy. The MLU can also be loaded with a digital comparator function or
any arithmetic calculation, e.g., summing, division, trigonometric functions,
The Model 2373 has four software selectable operating modes. The Strobed
Mode is the most commonly used mode. In this mode, the MLU is strobed by
the ECL Input Enable signals coming from previous logic unit(s). After
45 nsec, the output "word"
of the MLU becomes valid along with the four ECL Output Ready signals which
may be used to strobe the output word into other ECLine type modules. The
output word remains static until another Input Enable is received. Four
Input Enables are provided with an Enable condition being defined as their
coincidence (unused inputs are set to logical 1). This allows modules of
this type to be interconnected and operate asynchro nously (the Front Panel
slowest element controls the speed).
A second mode is the Transparent Mode where the Model 2373 operates at maximum
speed. This mode by passes the latch circuitry and thus provides a slight
speed advantage, offering a throughput time of only 40 nsec.
A third mode is the Pulsed Mode. This mode is used when it is desirable
to scale (count) any or all of the outputs. It insures that one and only
one pulse appears at any of the 16 outputs, provided that the output bit
is true for the given Input Word, when the Input Enable is made true.
Model 2371 - Data Register
Data: One 16-bit ECL input on front-panel 34-pin header with 110 ohm
input impedance. Maximum rate 100 MHz.
Input Enable: One input via front-panel 2-pin header. Enables the
Strobe signal. Minimum width 10 nsec. Unused input remains in the logical
Strobe: One input on 2-pin header. Input data word is latched on
leading edge of Strobe pulse. Minimum width 10 nsec.
Data: Two 16-bit ECL outputs on front-panel 34-pin headers. Input Data
are latched into two output ports, compatible with ECLine data bus structure.
Outputs are updated on receipt of an Input Strobe.
Data Ready: Two identical differential ECL outputs, each via a 2-pin
connector on front panel. Output becomes valid 60 nsec +10% after the leading
edge of the Input Strobe and remains valid until the leading edge of the
next Input Strobe. Other delay times may be set via the Delay Adjustment
potentiometer. See below.
Input-Output Delay: < 15 nsec from Input Strobe leading edge until
front-panel output data is valid.
Delay Adjust: Board-mounted potentiometer. Used to set the delay
between the Input Enable leading edge and the Output Ready leading edge.
Factory set to 60 nsec +10%. Adjustable over the range 30-90 nsec.
Power: 300 mA at +6 V, 1.7 A at -6 V (12 W total).
Model 2373 - Memory Lookup Unit
Input Word: One 16-bit ECL input on front-panel 34-pin header with 100
W input impedance. Maximum rate 22 MHz.
Enable: Four AND'd complimentary ECL pairs on front-panel header
into 100 W impedance. Unused inputs are logically true. Required only in
Strobe or Pulse Mode where Input Word is latched on leading edge of Enable
pulse (coincidence of Enable Inputs being used).
Output Word: One 16-bit complimentary ECL output from a front-panel
34-pin header. In the Strobe or Pulse mode, the content of memory address
given by the Input Word is presented 40 nsec after Input Enable. In the
Transparent mode, the content of the addressed memory is presented 40 nsec
after the Input Word.
Output Ready: Four complimentary ECL pairs from a front-panel header.
Provides Output Ready level for down -stream logic indicating a valid Output
Operating modes are set by CAMAC commands.
TRANSPARENT: Latching is disabled. Output follows changing input.
Output is invalid during propagation delay, between 5 nsec to a maximum
of 40 nsec.
STROBE: Input Word latched on leading edge of AND of Input Enables.
Ready appears 45 nsec after Enable.
PULSE: Same as Strobe Mode except that all true output bits go false
after a delay which is adjustable (20-150 nsec) via a front-panel potentiometer.
The purpose of this mode is to allow the scaling of individual bits of the
INHIBIT: Disables front-panel inputs. Used for programming memory
contents via computer.
Memory Configuration: Four 64K 4-bit Static RAMs make up the internal
memory allowing 16-bit x 16-bit operation. The memory in the Model 2373
has no battery back up and MUST be reloaded upon loss of power.
Computer Control: Read and Write Control Register (setting Mode and
Dimensionality); Read and Write Ad dress Register; Read or Write data at
address in Address Register; Read front panel input word or the output generated
by front-panel input.
PROPAGATION DELAY: In the Strobe and Pulse mode, propagation delay
is defined as the time between the leading edge (trailing edge for "OR"
condition) of the Input Enable signals at the front panel and the leading
edge of the Output Ready signals. This is factory adjusted to 45 nsec. The
Output Word settles at least 5 nsec before a true Ready condition, thus
allowing for proper set up time at the inputs to successive stages of other
LeCroy Programmable Data Handler Modules. In the Transparent mode, propagation
delay is defined as the time be tween the leading edge of the Input Word
at the front panel and the leading edge of the Output Word. This time is
solely a function of the static RAM chips and is at most 40 nsec.
Maximum Rate: Transparent Mode to 25 MHz. All Other Modes to 22 MHz.
Power Requirements: +6 V at 0.7 A; -6 V at 2.3 A; -6 V (via Y1 pin)
at 0.8 A. Note: -6 V is required on the Y1 pin to operate. (See CAMAC pin
Model 2371 - Data Register
X: An X = 1 response is generated for any valid CAMAC command.
F(0)·A(0): Read 16-bit word.
Model 2373 - Memory Lookup Unit
Please note that at power-on, the 2373 will NOT respond to any CAMAC commands
for one second, because of automatic programing of the Programmable Logic
X: An X = 1 response is generated for any valid FAN.
Q: A Q = 1 response is generated for F(16)·A(0) and F(0)·A(0).
A Q = 0 response is generated for these com mands when CAMAC Address Register
(CAR) reaches terminal count. This Q response is valid only when CAR has
been loaded via F(16)·A(1) after power up.
Z: Reprograms the programmable logic array which takes about a second.
The module will NOT respond to any CAMAC commands during this interval.
F(0)·A(0): Read 16-bit Output Word addressed by CAMAC Address
Register (CAR). CAR increments on S2. Inhibit Mode must be set.
F(0)·A(1): In Inhibit Mode, reads 16-bit CAR address. If NOT
in Inhibit Mode, reads 16-bit front panel Input Word.
F(0)·A(2): Read 7-bit CCR word that sets the mode of operation.
F(0)·A(3): Read 16-bit Output Word whose address is either the
latched Input Word (Strobe or Pulse Mode), CAR (Inhibit Mode) or unlatched
Input Word (Transparent Mode).
F(0)·A(4): Same as F(0)·A(1).
F(16)·A(0): Write 16-bit word into memory location addressed
by CAR. Requires operation in Inhibit Mode.
F(16)·A(1): Write 16-bit CAR address. Data word at ECL output
will change accordingly. Requires operation in Inhibit Mode.
F(16)·A(2): Write 7-bit CCR word that sets the Mode of operation.
Copyright© September 1995. LeCroy is a registered trademark of
LeCroy Corporation. All rights reserved. Information in this publicaction
supersedes all earlier