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32-CHANNEL DELAY AND LATCH MODULE
- Programmable Ripplethru®Delay: 300 - 682.5 nsec
- Edge Triggered Latch
- Prompt and Latched OR Outputs
- OR Carry
- Programmable Threshold
- Part of the PCOS III System
- Compatible with the 2735PC on Chamber Card
DELAYS AND LATCHES CHAMBER SIGNALS
The LeCroy Model 2731A has been designed as a central element for the PCOS
III MWPC encoding system. Each 2731A module accepts 32 differential ECL
inputs on two ECLine standard 17-pair front-panel headers. Using LeCroy's
unique Ripplethru delay, each signal input is delayed by a programmable
interval from 300 to 682.5 nsec. The delayed data are presented to edge-triggered
latches which can be activated by coincidence gates as short as 25 nsec.
Computer control of the threshold of chamber discriminators is provided
in the 2731A via an 8-bit digital-to-analog converter. This threshold programming
voltage is provided at both signal input headers. The LeCroy 2735PC chamber
cards use this voltage for setting the chamber threshold. See the 2735PC
data sheet in the chamber section for more details.
In order to account for the decision time of the trigger logic, the 2731A
contains a programmable delay. The delay of all channels of the 2731A module
may be set over the range 300-682.5 nsec in 1.5 nsec steps. The circuit
employed is LeCroy's Ripplethru circuit, a stable computer-controlled delay.
Unlike older mono-stable delays, it does not generate a dead time equal
to the delay. In fact, the Ripplethru can operate at > 10 MHz rates.
See Figure 1. Ripplethru provides the same high rate capability of cable
delay, yet also offers economy and program mability. Ripplethru also allows
the system to be configured without having to guess the trigger decision
time. The correct value may be programmed at run time.
Figure 1: Ripplethru Delay
The delayed chamber pulses are then latched by the 2731A if their leading
edge occurs during a gate pulse.
Two gate choices are distributed to the 2731A modules via the CAMAC Dataway.
A board-mounted jumper assigns Gate 1 or Gate 2 to the module. The programmability
of the gate allows timing variations within the system to be accounted for
under computer control.
The hit-wire data contained within the 2731A is stored as a 32-bit word.
The 2731As communicate to the 2738 PCOS III controller via 32-bit data transfers
at 10 times the maximum rate defined by the CAMAC standard. The 2731A provides
a LAM signal to allow only those modules containing hits to be read. Thus,
the PCOS III System requires a dedicated crate.
A 32-bit pattern may be downloaded into each 2731A, allowing selected inputs
to be tested by the 2738. This ability allows the 2731A-2738 encoding logic
to be completely exercised. The Model 2738 provides NIM-to-ECL conversion
and distributes the Test Signals via the Dataway. Coincidence Gates must
be provided with the appropriate delay.
The Model 2731A has a front-panel Delay Output, Channel 15 sampled at the
input to the latch, after the Ripplethru delays. This output offers a method
for manually setting the system timing and checking the Ripplethru. In addition,
each 2731A module offers a front-panel test point providing a test level
equal to the threshold programming voltage.
A reset pulse applied to the Model 2738 is distributed to the 2731A modules
via the Dataway. The action of this pulse is to clear the latches within
100 nsec. Then the PCOS III system is ready to accept another event.
The 2731A provides signals which allow the wire chambers to be used both
in the fast trigger and in the second level trigger decisions. The PCOS
III System also has been designed to be used with fast track recognition
For first-level trigger applications, the 2731A provides up to 16 Prompt
OR outputs. Internal wire wrap posts allow the user to pairwise wire-OR
the inputs before the Ripplethru delay. The 16 differential ECL outputs
(front-panel header) are compatible with LeCroy's growing ECLine family
of logic units.
For second-level trigger applications, the 2731A provides up to 8 latched
OR outputs. Levels are valid, within 50 nsec of the trailing edge of the
coincidence gate. Internal wire wrap posts allow the user to configure 4-fold
to 32 -fold Latched ORs on the OR output header along with the Prompt ORs.
INA, INB: 32 differential ECL inputs via two 17-pair front-panel headers.
Input impedance 112 ±2 ohm. Input configuration compatible with LeCroy
ECLine logic standard. Minimum pulse width 10 nsec.
Coincidence Gate: Two differential ECL inputs applied from the Model
2738 via the CAMAC connector. Board -mounted jumper selects input E1 or
input E2. Minimum width 30 nsec.
Test Input: Two differential ECL inputs applied from the Model 2738
via the CAMAC connector. Board-mounted jumper selects input E3 or input
E4. Minimum width 60 nsec. Applies a test input via the 32 pattern gates
to the Ripplethru inputs. Test level must be logical "zero" for
data acquisition. Model 2371A should be inhibited during Test.
Clear: Applied by the 2738 via CAMAC Dataway. Transmitted as an ECL
pulse. Clears all latches within 30 nsec. Minimum width 100 nsec.
Inhibit: Applied by the 2738 via the CAMAC Dataway. Common inhibit
line set via programmable bit in the 2738 disables all 32 ECL inputs. Should
be set when applying Test pulse.
RIPPLETHRU DELAY CIRCUIT
Delay Variations: ±5 nsec typical, ±10 nsec maximum channel
to channel and module to module.
Temperature Coefficient: Typically 100 psec/°C.
Range: 300-750 nsec in two jumper-selectable ranges; 300-682.5 nsec
and 330-750 nsec.
Programming: 8 bits, 1.5 or 1.65 nsec (jumper selectable) nsec steps.
Set via the Model 2738. Separate delay register per 2731A module.
Double Pulse Resolution: 100 nsec typically, 150 nsec maximum.
Delay 16: One front-panel output. Provides channel 16 logic signal
of amplitude ~ 5 mV after the Ripplethru delay. Used to check approximate
Ripplethru delay. Must be terminated in 50 ohm for correct output pulse
shape. May be unterminated when not in use.
Internal Delay: 500 kHz front-panel signal with low level width equal
to the delay setting. Amplitude approxi mately 25 mV into 50 ohm.
Threshold Programming: 8 bits 0.06 µA steps when used with the
2735PC. Set via the Model 2738. Separate threshold register per 2731A module.
Programming level and ground applied to the chamber cards via a single pair
of pins on each of the signal input headers. Pin 33 is ground and Pin 34
is the programmed level.
Threshold Monitor: A 2-pin header labeled THR on the front panel.
Provides a level of 0.5 V/µA when used with 2735PC.
Threshold Polarity Select: Internal wire-wrap option. Factory wired
OR Outputs: 16 differential ECL outputs. Internal wire wrap options
allow prompt or latched OR signal (1 to 32 -fold) to be connected to any
of the OR outputs.
Prompt OR Outputs: 32 open-collector OR signals preceding the Ripplethru
delay. Available on wire-wrap posts within the Model 2731A. May be arbitrarily
wired OR'd to the 16-position internal options connector. Signals are approximately
equal to the input width plus 35 nsec. Available within 30 nsec of the input.
Auxiliary Latched OR Outputs: Thirty-two open-collector OR signals
representing the status of each of the 32 latches. Available on wire-wrap
posts within the Model 2731A. May be arbitrarily wired OR'd to the 16-position
internal options connector. Levels are valid within 30 nsec of the trailing
edge of the coincidence gate.
Controls: Left most module must have termination of all control lines.
Termination via two 8-pin SIP resistor arrays. All modules shipped with
SIPs installed. See cut in the side panel for location.
Power Requirements: < 950 mA at +6 V; < 900 mA at -6 V; <
210 mA at +24 V; < 20 mA at -24 V. If prompt and latched ORs are not
required, ECL drivers may be removed, saving 400 mA at -6 V and 70 mA at
Packaging: In conformance with CAMAC standard for nuclear modules
(ESONE Committee Report EUR4100e). RF-shielded CAMAC #1 module.
Caution: Power up this module when a PCOS III System Controller,
Model 2738, is in the controller position.
Copyright© September 1995. LeCroy is a registered trademark of
LeCroy Corporation. All rights reserved. Information in this publicaction
supersedes all earlier