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The Model 2738 is the system controller for MWPC encoding with the PCOS III System. One Model 2738 CAMAC module occupies station numbers 24 and 25 of a dedicated crate filled with LeCroy Model 2731A (32-Channel Delay and Latch modules) for a maximum of 736 wires per crate. The 2738 system controller performs the readout, encoding, and control functions for the 2731A module and serves as an interface to the LeCroy DATABUS. Communication is achieved via either a LeCroy Model 4299 DATABUS Interface and Memory Module which is resident in the CAMAC data acquisition system or a user-supplied fast ECL interface using the Model 2738 ECLport out connector.


The Model 2738 offers both ECLport readout encoding and data compacting at 10 megawords/sec, 10 times the maximum CAMAC data transfer rate. It determines the addresses of all wires which were hit and then stores these addresses in a 1K by 16 buffer memory which is interfaced to the LeCroy DATABUS for lower rate trans mission of the hit wire addresses via the Model 4299. Internal switches in the Model 2738 allow the implementa tion of a hard-wired cluster centroid calculator. In this mode of operation, the address of the cluster centroid (14 bits) and the width of the cluster (4 bits) are transmitted as successive data words. The internal switches deter mine whether clusterized or unclusterized data is available at both the DATABUS port and the ECLport.

The ECLports of the 2738 PCOS III System Controller can be used for both cluster calculations that transcend dedicated crate boundaries and track recognition logic. Master/Terminal switches set the status of each 2738 module in a multi-crate system. Cluster calculations transcending a crate boundary can then be achieved by connections between the ECLport OUT and ECLport In of the crates in question. If all of the crates in a PCOS III System were connected together via the ECLports, the master crate (the crate closest to the Model 4299) be comes a master controller. Even with this arrangement it is still possible to communicate to the track recognition logic via the ECLport OUT of the master crate.

The 2738 accepts NIM control signals and distributes them to the 2731A modules via the CAMAC Dataway. The system accepts four control lines: E1, E2, E3, E4 and a bridged high impedance Clear Input. The receiver mod ules may be assigned to the control lines via internal jumpers.

The value of the chamber discriminator card thresholds (LeCroy Model 2735PC) the value of the delay settings for the LeCroy Model 2731A Delay and Latch, the module addresses for the Model 2731As, and the test patterns are transmitted as datawords from the data acquisition system via the LeCroy Model 4299 DATABUS Control Module to the PCOS III System Controller. This protocol allows the user to determine chamber plateaus, to optimize the required delay ("electronic cable cutting") to assign any 9-bit address to any 2731A module for complete system control, and to OR a test pattern with the Model 2731A wire inputs for systems tests.

Figure 1: Block Diagram of the Model 2738

Figure 2: Interconnecting PCOS III crates with ECL bus for interconnection in triggering system or higher speed data acquisition



E1, E2, E3, E4:
NIM Level Inputs ( -600 mV). Input impedance 50 W; selection of E1, E2, E3, E4 via jumper option in receiver modules; trailing edge of E1 initiates encoding. See receiver module specifications for minimum widths and usage.

Clear Encode: NIM Level input ( -600 mV) clears the encoder section of the Model 2738 and 2731A latches within 100 nsec. High impedance front-panel bridged Lemo pair suitable for daisy chain operation. May be applied at any time. Minimum width 100 nsec.

INH Encode: NIM level input ( -600 mV) prevents encoding; may not be asserted after encoding has begun. High impedance front-panel bridged Lemo pair suitable for daisy chain operation.

Busy Encode: NIM level output ( 16 mA) indicates encoding in process. Lemo connector bridged suitable for daisy chain to indicate total system status. Busy is asserted 100 nsec after the trailing edge of gate 1 until the encode cycle is complete.

Reset: NIM input ( -600 mV) clears Model 2731A latches and 2738 memory within 100 nsec. High impedance front-panel bridged Lemo pair suitable for daisy chain operation. If applied during DATABUS readout, the Model 4299 must be reset via its RT input.


Address: Four, 2-position switches, #1, 2, 3, 4. Defines the address of Model 2738 for communication via DATABUS. Address = 4321. "Open" = "1".

LAM Enable: Two-position switch, #5. Generates LAM Request in 4299 at end of readout cycle. "Closed" to disable LAM Request.

DATABUS Control: Two position switch, #6. Automatic readout of the data in the buffer memory to the Model 4299. The 2738 local memory can be at any time read by using the 2738 Reread Command. "Closed" for automatic readout.

Terminal: Two Position Switch, #7. Turns on the front-panel "Terminal" LED. This LED indicates that this controller is furthest from Master. It serves to terminate Data Encoding. If there is no ECLport daisy chain, both Master and Terminal switches must be on. "Closed" turns on Master LED.

Master: Two Position Switch, #8. Turns on the front- panel "Master" LED. This indicates that this controller processes all data on the ECLport daisy chain and stores the data for readout. "Closed" turns on Master LED.

ECLport Source: Two position switch, #9. Selects data before or after Data Pipeline. "Closed" to select data before Data Pipeline.

Pipeline Mode: Two position switch #10. Enables the clusterizing mode of the Data Pipeline. Internal memory always reads the output of the Data Pipeline. "Closed" for non-clusterizing mode.

Data Ready: NIM level (> 16 mA) indicates data at ECLport are valid. Data Ready is asserted 30 nsec after ECLport data are valid.

Data ACK: NIM level ( -600 mV) inhibits data transfer to ECLport. Left open, data appears at ECLport at 10 megawords/sec. If Data ACK is driven to the 0 mA state for 20 to 80 nsec, one word is transmitted to ECLport output. If Data ACK is the 0 mA state for > 80 nsec, > 1 word may be presented at ECLport.

ECLport In: 17-pair header; accepts 16-bit differential ECL signals from ECLport out of the previous Model 2738 in an ECLport chain.

ECLport Out: 17-pair header provides 16-bit differen tial ECL signals in same format as CAMAC data, see below (delimiter word not transmitted). Output configu ration defined by the ECLine standard.


Commands via the DATABUS cable are based upon simple binary coding as follows:

Symbol Definitions:

A : 4-bit Controller Number A1 - A4

S : 9-bit Logical Address: S1 - S9

N : 5-bit CAMAC Station: N1 - N5

V : 8-bit Register Value: V1 - V8

R : 3-bit Register R1 - R3

X : Don't Care

Consult the DATABUS Interface Manual for details of data transfer.

Wire Inhibit: Disables all data inputs. Used during exercise of test pattern. I = 1 implies wire inhibit. I must be maintained in all subsequent command words.

Assign Logical Address: Transmit 3 words:

Word 1:

Word 2:

Word 3:

Module Write: Eight-bit value, V, sets Threshold, Delay, or pattern. Transmit 3 words.

Word 1:

Word 2:

Word 3:

Register (R) ­p; Description

0(000) ­p; Delay 300-682.5 nsec in 1.5 nsec steps.

1(001) ­p; Threshold 0-15.3 µA in 0.06 µA steps.

2(010) ­p; Test patterns wires 0-7.

3(011) ­p; Test patterns wires 8-15.

4(100) ­p; Test patterns wires 16-23.

5(101) ­p; Test patterns wires 24-31.

Reread Command: Causes transfer of present contents of buffer memory to the Model 4299.

Word 1:

Master Reset: Used to clear 2738 and enable for data taking. Initiated by F(9)·A(0)+(1) applied to Model 4299.


Returns wire address, W, plus logical module address S. Wire address includes "half wire" bit, h, from centroid calculation. H is width of Cluster.

Clusterized Data:




Non-Clusterized Data:


: address

: address



Power Requirements: 5.3 A at +6 V; 1.0 A at -6 V.

Packaging: In conformance with CAMAC standard for nuclear modules (ESONE Committee Report EUR 4100e). RF-shielded, CAMAC #2 module.

Copyright© September 1995. LeCroy is a registered trademark of LeCroy Corporation. All rights reserved. Information in this publicaction supersedes all earlier