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NIM-T0-QVT MULTICHANNEL ANALYZER INTERFACE
1691B PC-TO-SIB INTERFACE CARD
- NIM or CAMAC Compatible
- Interfaces the QVT to VME or a PC
- Uses a High Speed Parallel Bus
- Demo Software Provided
INTERFACES THE QVT MCA TO VME OR A PC
LeCroy's NIM Model 3031 qVt Interface has been designed to allow the Model
3001 qVt Multichannel Analyzer to be remotely controlled from an external
computer. Communication with the host computer is accomplished over the
LeCroy System Interface Bus (SIB), a high speed parallel bus in use on several
LeCroy modules. This bus uses a 60-pin flat cable to connect the 3031 to
either a PC-compatible computer or to a VME system. The PC must have a LeCroy
Model 1691B card housed in an expansion slot of the PC. With a VME system,
an 1131 VME-to-SIB interface is required. The Model 3031 allows the qVt
to be used for calibration and setup as well as for display during the operation
of an experiment.
Data in the 3001 is organized into 16 bit words. The 3031 allows this memory
to be written into from a PC via a 1691B card or from a VME system via an
1131 VME to SIB bus interface. The data in the qVt's memory may be displayed
on a standard x-y scope or read out to a computer and plotted on the CRT
Included with the Model 3031 is an example PC program which allows for the
reading of data as well as control of most of the qVt's functions. Data
from the qVt's memory may be saved to disk in an ASCII format. Previously
saved files may be recalled from disk and downloaded to the qVt. This example
program is intended only to illustrate methods of programming and will aid
in the development of application specific software.
An increment feature allows any channel of the qVt to be incremented by
one. This feature allows use of the analyzer as a histogram and display
module when used with an x-y scope.
The Model 3031 contains an incrementing address register which may be loaded
from the SIB bus. The value contained in the register is used to address
memory for both read and write operations. After the read or write operation
is performed, the address will be incremented by one providing the auto
increment bit is on. This feature is useful when reading the entire memory
Note that the Model 2301 is available to read out the qVt from CAMAC. See
the separate data sheet for details.
Requirements: For use with a PC-compatible host, the LeCroy Model 1691B
must be installed. If the host interfaces to a VME system, then the LeCroy
Model 1131 must be used in the VME crate.
Inputs and Outputs: Communication from host computer to front-panel
SIB port is via a 60-pin high density cable. (This cable is purchased separately
with part number DCSIB/60-L, where L = length in feet.) Communica tion with
the 44-pin qVt interface connector is implemented using a 60-pin flat cable
and a LeCroy 60-pin to 44 -pin convertor card.
General: A sample "C" language program written for a PC
SIB PORT COMMANDS
W0: Write 6 bit control word.
- D0 ­p; Auto increment. Set the auto increment bit so any read
or write cycle to the qVt will increment the address counter by one.
- D2 ­p; Start qVt. Arm the qVt for data acquisition.
- D3 ­p; Stop qVt. Stop qVt data acquisition.
- D4 ­p; Clear qVt. Clear entire qVt memory.
- D5 ­p; Increment address. Increment the address register by
W1: Write to internal address latch. This address will be used for
the next read, write or increment of the qVt.
W2: Write data to the qVt using the address stored in the internal
W5: Increment the value of the qVt data memory using the address
stored in the internal address latch.
W6: Transfer data from the qVt to the 3031's internal data latch
using the address stored in the internal address latch. This command is
usually followed by an R2 read of the internal data latch.
R0: Read back status of control register.
- D0 ­p; Auto increment bit. 1 = Auto increment on.
- D2 ­p; Status bit. 1 = qVt in acquisition mode.
- D3 ­p; Overflow bit. 1 = qVt has reached terminal count (65535).
Overflow bit is latched in the 3031 and cleared when clear qVt is issued.
- D4 D7 ­p; Module address. D7 = MSB, D4 = LSB.
R1: Read back value of internal address register.
R2: Read internal data latch. This command is usually preceded by
a W6 transfer of data from the qVt to the internal data latch.
R3: Read value of most recent conversion.
Signal Levels: All connector signals are TTL levels.
Data Format: 16-bit word on data cable, built from two 8-bit host
transfers. Bidirectional data is accompanied by four Module Address and
four Register Address lines driven from the 1691B to the connected device.
Data Rate: Each transfer is initiated by a positive going TTL strobe
from the host. Therefore, the rate is depen dent upon host computer speed
and cable length. Typical speed using an 8 MHz, IBM PC-AT driving 2 meters
of cable is 2 MB/sec.
Signals: Active low TTL RD, WR, ENB, and BYP for use with the 1821
are driven by the 1691B.
Compatibility: IBM PC compatibles with 80286 or higher performance
ADP-SIB34/60: Adapter board required when using the 1691B.
DCSIB/60-L: 60-pin, high density cable from the 3031 to the 1691B
or 1131. Specify the length in feet (maximum 30 feet).
Copyright© September 1995. LeCroy is a registered trademark of
LeCroy Corporation. All rights reserved. Information in this publicaction
supersedes all earlier versions.