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LeCroy Models 6840 and 6841 Dual Channel Waveform Digitizers provide the system core for high speed, high density, long memory waveform recording. The 6840 and 6841 each feature a 2 channel single card architecture that delivers unmatched channel density (up to 46 channels) in a 19 inch rackmount.

The 6840 simultaneously digitizes both channels at speeds of up to 40MS per second with 8-bit resolution, providing 128 kS of non-volatile memory per channel. The 6841 simultaneously digitizes both channels at speeds of up to 100MS per second, providing 128 kS of memory per channel.

Advanced design and manufacturing methods ensure low cost expansion and maintenance. The minimum two channel digitizing system contains one 6840 or 6841, a bench top or rack mount mainframe and a GPIB interface module. To add more channels, just insert more 6840 family digitizers into any open mainframe slot. The optional 6103 amplifier provides high sensitivity to capture signals with 200 µV resolution on 50 mV full scale.


Unmatched Channel Density

Surface Mount Technology (SMT) and custom monolithic memory management circuitry provide the 6840/41 with greater component density than ever before available. Each channel uses an independent A/D converter and memory to enable full sampling speed. Each module uses a common timebase and triggering section. External clock and trigger inputs allow multiple digitizer synchronization to the experiment, while clock and outputs can drive additional channels.

Long Recording Time

LeCroy digitizers lead the market in long memories. The 6840 and 6841 each feature 128 ksamples per channel of built-in memory in a single-wide two channel design. Long digitizer memory ensures capture of the entire transient signal without slowing the digitizing speed or missing important details. The 6840/6841 digitizers also contain complete pre-trigger sampling capability for viewing events that caused the trigger. Sampling can be held off 16 to 128K clock periods after the trigger, which can be useful for capturing radar or sonar returns.

Segmentable Memory

For multiple fast triggering events, host control software allows memory segmentation in the 6840/6841. Each segment contains one trigger event. Up to 4096 segments, each with pre- and post-trigger data, record events on the fly. Trigger repetition rates up to 25kHz can be achieved with a dedicated host controller by using segmentable memory to minimize dead time caused by data read out after each capture.

Fully Programmable Set-up

All 6840/6841 controls are programmable. Sampling speed, offset, memory size, and triggering adjustments are fully programmable in a series of simple commands. Two readout modes are available. Two-channel readout mode enables data transfer from both Channels 1 and 2 simultaneously, minimizing transfer time to the host computer. Single-channel readout mode enables data transfer from either Channel 1 or 2.

PC Software For Control and Analysis

The 6840/6841 family's IEEE-583 Standard (CAMAC) design is compatible with LeCroy Module 8901A and 6010 GPIB-to-CAMAC controllers, as well as other IEEE-583 standard controllers.

LeCroy supports the 6840/6841 Dual Channel Waveform Digitizers with National Instruments LabWindows Instrumentation Software (Model 6930) for the PC. LabWindows provides data acquisition, display, and analysis capability for the LeCroy instruments including the 6840/6841 series. The Model 6930 includes National Instru ments Standard and Advanced Analysis Libraries and LeCroy's Model 6930-LW Instrument Driver Library with software drivers for LeCroy instruments. With LabWindows, the user can tailor a fully integrated acquisition and analysis system that can include a variety of other IEEE-488 instruments such as function and pulse generators. The analysis capability includes FFT, smoothing, curve fitting, statistics, and more. Both C and Basic software languages are supported and example programs are supplied for all LeCroy digitizers.


Analog Input

Two channels per module.

Connector: BNC type coaxial.

Impedance: 50 ohm, ±3% typical.

Bandwidth: DC to 100 MHz.

DC Offset Voltage: Programmable over ±510 mV with 255 µV resolution, 5 mV tolerance.

Coupling: DC.

Overload Recovery: ±1% F.S. in 25 nsec from 1.5X overdrive pulse of < 1 µsec duration.

Overload Protection: ±2.5 V DC input, ±500 V pk for 30 nsec with 50 ohm source.

Channel-to-Channel Isolation: > 50 dB isolation between channels for full scale input at 100 MHz.

Analog-to-Digital Conversion

Input Amplitude Range: 510 mV p-p (2 mV/LSB) ±1% full scale.

Single Shot Resolution: 8 bit (offset binary code).

DC Accuracy: 2% full scale.

Dynamic Accuracy:

6840 Dynamic Accuracy Chart

6841 Dynamic Accuracy Chart


6840 Sample Clock Rates:
40 MS/sec, 20MS/sec, 10 MS/sec, 8 MS/sec, 5 MS/sec, 4 MS/sec, 2 MS/sec, 1 MS /sec, 500 kS/sec, 400 kS/sec, 200 kS/sec, 100 kS/sec, 80 kS/sec, 50 kS/sec, 40 kS/sec, external.

6841 Sample Clock Rates: 100 MS/sec, 50MS/sec, 25 MS/sec, 20 MS/sec, 12.5 MS/sec, 10 MS/sec, 5 MS /sec, 2.5 MS/sec, 2 MS/sec, 1.25 MS/sec, 1 MS/sec, 500 kS/sec, 250 kS/sec, 200 kS/sec, 125 kS/sec, 100 kS /sec, external.

Accuracy: 0.01% crystal oscillator.

External Clock: Any frequency input up to 40 MHz (100 MHz for 6841); threshold level programmable over ±2 V in 256 steps; BNC type coaxial connector.

Clock Out: ECL output, capable of driving 50 ohm to ground. BNC type coaxial connector.


Trigger Input:
Slope +/- programmable; BNC type connector.

Level: Variable level (±2 V) programmable in 256 steps; accuracy 3%; BNC type coaxial.

Impedance: 50 W ±3%.

Bandwidth: DC to 100 MHz.

Minimum Trigger Width: 10 nsec.

Overload Protection: ±2.5 V DC; ±250 V pk for 1 µsec with 50 ohm source.

Trigger Output: ECL, capable of driving 50 ohm to ground; BNC type coaxial connector.

Waveform Memory

Waveform Memory:
128 ksamples per channel.

Active Memory Size: Programmable from 16 samples to full length in 16 sample increments.

Pre-trigger: Memory can be divided into pre- and post-trigger sample storage; programmable from 0 to 100% in 16 sample increments.

Memory Segmentation: Memory segmentable into 4096 segments for all memory configurations. Segment size programmable from 16 samples to maximum memory in 16 sample steps; segment advance provided by external software control.

Battery Backup: Data in memory preserved when external power removed.


Status Indicators:
Two front panel LEDs indicate CAMAC access/power and armed/triggered.

Front Panel Connectors: BNC type; CH1 input, CH2 Input, Trigger Input, Trigger Output, Clock Input, Clock Output.

Battery: Replaceable lithium battery supplies power for memory back-up for > 6 months.


RF-shielded module in conformance with IEEE-583 Standard (CAMAC).

Power Requirements:

Click here for power chart

Module ID: Software command query provides identification for module; 6840 ID is 4, 6841 ID is 5.


Operating Temperature:
+15° to +25° C intake air with sufficient airflow to maintain exhaust air less than 15° C higher than intake; up to 30° C if exhaust temp. < 40° C.

Storage Temperature: -10 to +50° C.

Operating Humidity: Up to 90% r.h. non-condensing at +25° C.

Operating Altitude: < 10,000 feet above sea level.



Read Clock Rate Register.

F(0)·A(1): Read Valid Sample Register (read only).

F(0)·A(2): Read Coarse Channel 2 Offset.

F(0)·A(3): Read Fine Channel 2 Offset Adjust.

F(0)·A(4/5): Read Input Gain Channel 1/2.

F(0)·A(6): Read Trigger Threshold.

F(0)·A(7): Read External Clock Threshold.

F(0)·A(8): Read Coarse Channel 1 Offset.

F(0)·A(9): Read Fine Channel 1 Offset Adjust.

F(1)·A(0): Read Memory Address Counter.

F(1)·A(1): Read Trigger Address Latch.

F(1)·A(2): Read Circular Buffer Counter.

F(1)·A(3): Read Segment Size Register (write only).

F(1)·A(4): Read Pretrigger Hold-off Counter.

F(1)·A(5): Read Post Trigger Counter.

F(1)·A(6): Readout Size Counter.

F(2)·A(0): Read Channel 1 and 2 Memory Data Access.

F(2)·A(1/2): Read Channel 1/2 Memory Data Access.

F(3)·A(0): Read Module ID Word.

F(8)·A(0): Test LAM set and Enable.

F(9)·A(0): Arm.

F(9)·A(1): Abort and set the module in known state.

F(10)·A(0): Clear LAM.

F(16)·A(0): Write Clock Rate Register.

F(16)·A(1): Write Valid Sample Register (read only).

F(16)·A(2): Write Coarse Channel 2 Offset.

F(16)·A(3): Write Fine Channel 2 Offset Adjust.

F(16)·A(4/5): Write Input Gain Channel 1/2.

F(16)·A(6): Write Trigger Threshold.

F(16)·A(7): Write External Clock Threshold.

F(16)·A(8): Write Coarse Channel 1 Offset.

F(16)·A(9): Write Fine Channel 1 Offset Adjust.

F(17)·A(0): Write Memory Address Counter.

F(17)·A(1): Write F(17) Start Segment Address, F(1) Trigger Address Latch.

F(17)·A(2): Write Circular Buffer Counter.

F(17)·A(3): Write Segment Size Register (write only).

F(17)·A(4): Write Pretrigger Holdoff Counter.

F(17)·A(5): Write Post Trigger Counter.

F(17)·A(6): Write Readout Size Counter.

F(18)·A(0): Write Channel 1 and 2 Memory Data Access.

F(18)·A(1/2): Write Channel 1/2 Memory Data Access.

F(24)·A(0): Disable LAM.

F(25)·A(0): Computer Trigger.

F(26)·A(0): Enable LAM.

F(27)·A(0): Test LAM set.

Copyright© September 1995. LeCroy is a registered trademark of LeCroy Corporation. All rights reserved. Information in this publicaction supersedes all earlier versions.