MULTIHIT TIME-TO-DIGITAL CONVERTER WITH DATA SUPPRES SION
- Suitable for Use with a Multi-Ranging ADC Front-Ends
- Programmable Sparse Data Readout
- Built-in Data Zero Suppression
- High Density, 96 Channels Per VME 9U Slot
- 500 psec LSB
- Programmable Full Scale up to 32 µsec
- Up to 16 Hits/Channel (Programmable)
- Rising and/or Falling Edge Timing Information
- < 20 nsec Double Pulse Resolution
- Fast Conversion
- Multiple Event Buffer, 16 Events
- Capable of MBLT
- Supports Multi-Module Data Transfer Specification (CBLT/MCST)
- Built-in Self Test
HIGH RATE TDCs FOR WIRE CHAMBER SPECTROMETERS
The VME Model VT960 is a 96-channel, high resolution, multihit TDC designed
for high rate experiments. This TDC provides precise time measurements for
spectrometers and hodoscopes consisting of multiwire propor tional, drift
or time projection chambers. With a least count of 500 psec and a 16-bit
range, the Model VT960 can measure time intervals up to 32 µsec duration.
The instrument operates in Common Start or Common Stop modes. Common Stop
Mode eliminates the need for expensive delay cables normally required for
each input channel of a fixed target experiment.
The VT960 provides the high performance, high density, versatility, and
automated test features required for large scale experiments.
The VT960 uses the new VME64 standard (ANSI/VITA 1-1994) which was developed
in 1994 by the VME International Trade Association (VITA). Applying this
VME64 standard and a 9U style card makes it a very powerful and universal
TDC which can be housed and operated in an entirely VME environment.
The individual channel inputs are located on the front panel. They accept
differential ECL signals and are termi nated in 110 ohm. The COMMON input
(Common Start or Stop) also accepts ECL signals and has a removable 110
ohm termination. By removing this termination, the COMMON signal(s) can
be cascaded, as long as the termination in the last module of a block of
modules is left in place. This scheme eliminates the extra propagation delays
caused by embedded repeaters and leaves only the very slight delays due
to the cables cascading the individual modules (approximately 50 psec/cm).
The input can also be configured to be current driven by applying ECL voltage
levels at the inputs. This mode is optional and can be set by jumpers.
Data from the VT960 is automatically zero suppressed. Readout can be done
either like a FIFO or by directly addressing the data address space A32.
Each data event is organized as a header word followed by a variable number
of data words. The header word contains the event number word count as well
as address (logical /geographic). Each data word contains the geographic
address, channel number and hit count as well as the data recorded.
At the heart of the VT960 lies the MTD133B Monolithic Time Digitizer, an
8-channel, 16-bit dynamic range TDC circuit with 500 psec least count. Arrival
times can be recorded for either the rising, falling or both edges. The
double pulse resolution is 20 nsec.
The MTD133B uses a high-speed clock, a continuously counting scaler, and
a three state interpolator. When a pulse arrives, the contents of the scaler
and interpolator are stored in memory. Up to 16 words of data can be stored
in the LIFO (Last In First Out memory) for each channel. During readout
each of the stored signal times is automatically subtracted from the COMMON
hit time. Therefore, the output is the actual time difference with virtually
no pedestal. The difference value is further compared to a programmable
upper threshold and discarded if it is greater than this threshold. This
threshold is programmable from 8 nsec to 32 µsec with a resolution
of 8 nsec.
In this way the MTD133 accommodates many different, difficult measurement
scenarios. For users who wish to detect only pulses coming within the drift
time of the chamber, the programmable threshold produces a program mable
full scale. In addition, the user can program the depth of the LIFO from
1 to 16 hits, thus creating a guaran teed, not to exceed, conversion time.
VT960 BLOCK DIAGRAM
Control registers configure the TDC to report either the time of the rising
edges, falling edges or both, facilitating pulse width measurements. Test
functions allow verification of each channel's behavior. Full scale time
out in the COMMON START mode can either be programmed or supplied externally.
MULTIPLE EVENT BUFFER
The module contains an 16 event buffer. This digital memory buffer provides
two primary advantages. First, dead time in the experiment is reduced because
data readout can be done during the acquisition of subsequent events. Second,
the event data can be stored temporarily while the trigger decision to read
or discard the event is made. Events in the buffer are discarded with a
VME command to skip the event. This skip command causes an internal read
pointer to increment, positioning the next event at the top of the readout
queue. As each event is recorded, a modulo 16 event tag number is appended
to it in order to allow the coherence across multiple modules to be verified.
MULTI-RANGE ADC COMPATIBILITY
The VT960 provides the features necessary for interface and readout of single
and multi-range charge-to-time converting front ends. The VT960 then provides
the time encoding function and VME readout of the charge signal. The charge-to-time
converters always generate an output pulse, even at pedestal so that non-zero
time data is recorded by the VT960 on every channel. By being able to encode
both input edge polarities, widths of pulses
can be encoded.
In a mode similar to the LeCroy FASTBUS Model 1881M and 1877S, a sparse
data readout scheme can be used to prevent unwanted data from being buffered.
The VT960 allows the user to program 96 constants, one per channel, which
can be compared to the measurement values. Data exceeding these individual
thresholds is buffered reducing both the dead time and quantity of data
that must be transferred over VMEbus to the host computer. See Figure
When the VT960 is used in a multi-range ADC application, the TDC is programmed
to operate in Common Start mode. The Common Start timeout (as appropriate
for the desired full scale and resolution) can be selected by configuration
at the TDC's CSRs.
A two bit hit count field has been provided in the VT960 data word format.
This indicates (modulo 4) how many hits were recorded in the channel's LIFO.
By using the VME-controlled readout depth parameter it is possible to readout
only 1 word per channel, while also knowing the total number of hits on
that channel. This feature pro vides a second level of data reduction from
the multi-range QADC so that only 1 data word per channel is necessary.
Inputs: 96 ECL differential line receivers. Input impedance 110 ohm
±10%. Minimum pulse width 10 nsec FWHM. Input swing 400 mV, differential.
Jumper option provides diode on input to allow for current drive.
Least Significant Bit: 500 psec.
Total R.M.S. Error: 400 psec (Note: The R.M.S. of a gaussian distribution
is equal to sigma), 300 psec typical.
Full Scale: 0 to 32.768 µsec, ±0.0025%; programmable via
CSR18 in steps of 8 nsec.
Pedestal: 14 to 20 counts.
Double Edge Resolution: The VT960 can measure two edges separated
by as little as 10 nsec. No two pulse edges should be closer than 10 nsec.
This implies a lower limit on the double pulse resolution of 20 nsec.
Common Start/Stop: Front-panel differential ECL input or via PØ
on backplane, SG, SG* differential ECL, selected by jumpers, 110 ohm termination.
Fast Clear Window (FCW): Starts at end of Time Out (Common Start)
or at Common Stop. Can be programmed 1024 nsec to 512 µsec. During
this period, the user can apply a FAST CLEAR to discard the event just captured.
Zero Suppression: Automatic for channels that have no hit.
Long Term Stability: < 100 ppm/year.
Temperature Coefficient: < 10 ppm/°C.
Differential Non-Linearity: Maximum ±0.2 LSB (±0.1 LSB
Integral Non-Linearity: < 25 ppm full scale.
Fast Clear: Differential ECL input via a 2-pin front-panel connector
(removable termination resistors) or via backplane Paux CL, CL* differential
ECL line. Minimum pulse width 40 nsec.) When applied during the FCW, clears
data in the current event and readies module for acceptance of a new event.
Fast clear settling time is < 250 nsec. Fast Clear is leading edge sensitive
and must be performed during FCW.
Time Out: Differential ECL input via a 2-pin front-panel connector.
Minimum width 50 nsec. In Common START mode, terminates measurement in progress
and starts conversion.
Busy Output: Differential ECL output via a 2-pin front-panel connector.
Indicates the module is converting hit information. The unit is unavailable
for data capture. Stays true when buffers are full.
Conversion Time: 1.2 µsec + 50 nsec per hit within the programmed
full scale; 1.75 µsec minimum.
On-Board Tester: The tester generates square wave pulses (nominally
50% duty cycle) for functional testing. The pulse trains can have 1, 2,
4 or 8 cycles with half periods of 125, 250, 1000 nsec or 2000 nsec.
Multiple Event Buffer: The digital data memory is logically organized
as a circular buffer, large enough to store the results of up to eight events.
Front-Panel Indicators: Activity Power: Yellow LED indicates module
is being addressed. COMMON: Bicolor LED indicates whether Common Start/Stop
Power Requirements: 5 V at 5.0 A, -5.2 V at 4.0 A, -2 V at 3.0 A,
12 V at 100 mA, -12 V at 100 mA.
Packaging: Single-width VME module (ANSI/IEEE-960-1989).
Buffer: Bicolor: green indicates valid data in multievent buffer,
red indicates buffer full.
Copyright© September 1996. LeCroy is a registered trademark of LeCroy
Corporation. All rights reserved. Information in this publicaction supersedes
all earlier versions.