Click model number for photo



The MQS104A is a bipolar monolithic, 4-channel preamplifier optimized for proportional chamber applications. Integrated on the chip with the preamplifier is a 4-pole shaping amplifier. The impulse response is an 18 nsec wide pulse with 10 nsec rise time and 18% undershoot. This is a good match for a typical proportional chamber (30 nsec drift time) and results in a 50 nsec wide output pulse with no undershoot. The MQS104A is packaged as a 28-pin PLCC for high density surface mount printed circuit boards.

The differential output has a quiescent DC level of 7 V, and less than 0.5 V offset. The output is intended to be AC coupled to a differential comparator or discriminator. The threshold can be as low as 1 fC (15K electrons). The differential output is linear up to 32 fC (200K electrons) input impulse charge. Inputs up to 64 fC saturate only the output stage, allowing immediate recovery without disturbing the tail cancellation. The input DC level is self biased to 0.7 V allowing simple protection circuits and direct connection to a proportional chamber sense wire floating near ground. The input should be driven from a very high impedance source (typically a collection wire or pad).


Power Supplies: 37 mA typical, 50 mA maximum at +10 V; 19 mA typical, 24 mA maximum at +5 V; 10 mA typical, 13 mA maximum at -2 V; Total dissipation 485 mW typical.

Charge Gain: 4.3 µV typical (27 mV/fC) ±30%.

Input Impedance: 230 ohm, ±30% at 10 MHz.

Output Impedance: 90 ohm, ±30%.

Maximum Input Signal for Linear Output: 200K electrons (32 fC) with no load on outputs.

Noise (RMS): < 3000 electrons (0.4 fC) typical with 20 pF on input.

Impulse Response: 10/90 rise time 10 nsec; pulse width (FWHM) 18 nsec; undershoot 18%, 80/20 undershoot recovery 30 nsec. All time specifications are ±30% measured with 2 pF injection capacitor.

Adjacent Input Crosstalk: 2% maximum (with open circuit output).

Crosstalk to Non-Adjacent Inputs: < 1% typical < 2% maximum.

Quiescent Output Level: 7 V DC ±1 V.

Differential Output Signal: < ±500 mV DC offset.

Input Bias Voltage: +0.7 V (internally generated).

MQS104A Pin Out Diagram

The MQS104A normalized response to a capacitively coupled voltage step with measurements illustrated. Click here for graph.


Gain vs. Input Capacitance Graph

Gain vs. Input Pulse Rise Time Graph

Equivalent RMS Input Noise vs. Input Capacitance Graph

Output Noise vs. Input Capacitance Graph

Input Impedance vs. Frequency

Noise Test Setup Diagram. All power supplies decoupled to ground by a 0.1 µF capacitor.

Gain Test Setup Diagram. All power supplies decoupled to ground by a 0.1 µF capacitor. Gain vs. capacitance used square pulse with rise time of 0.9 nsec into varying capacitance. Gain vs. rise time used fixed injection capacitance of 1.8 pF.

Typical circuit using MQS104A (MQS104TB demonstration board) Diagram.

Copyright© September 1995. LeCroy is a registered trademark of LeCroy Corporation. All rights reserved. Information in this publicaction supersedes all earlier versions.