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The PCOS 4 Proportional Chamber Operating System has been designed to provide complete instrumentation for Multiwire Proportional Chambers (MWPCs) in nuclear physics, heavy ion and elementary particle physics experiments. This cost-effective, on-chamber, high density system supports a wide range of chamber opera tions and multi-level triggers. The system can be controlled and read out via CAMAC (IEEE-583) or VME.


A New Proportional Chamber Readout System

Proportional chambers are one of the workhorses of particle physics experiments. The readout electronics has evolved over more than 2 decades of experience. PCOS 4 is the latest and most highly integrated commercially available readout system.

PCOS 4 is a complete Multiwire Proportional Chamber Operating System based on the experience gained with previous PCOS Systems. PCOS 4 contains the circuitry to amplify, discriminate, delay, latch and encode multiwire proportional chamber signals, all on a single chamber-mounted card! High performance and simplicity are achieved through the use of just two custom integrated circuits, a preamplifier and a delay and coincidence integrated circuit. Readout and control of the system is provided by additional CAMAC or VME controller and driver modules.

The PCOS 4 System is chamber-mounted and has an integrated delay circuit providing usable delays from 400 nsec to 800 nsec. This feature eliminates the need for signal cables either to bring the signals to the cards or to delay the signals for coincidence timing. In addition, logical streams of 256 channels are read out through one master card via one 8 twisted pair cable which is a reduction of 32 times over previous systems (one twisted pair/wire).

Physical Configuration

The physical packaging of this integrated system is dependent on the experimental requirements and is de signed to be easily modified to accommodate different chamber designs. See Table 1 for a comparison of available chamber cards.

Table 1

The Model 2741-16Y is shown in Figure 1. This 4.5" by 10.375" board contains everything required for 16 wires, including the input protection circuitry. The input connector (36-pin, 0.156" pitch) and the readout connector (36 -pin, 0.100" pitch) are on the same edge of the board, simplifying installation and maintenance. This board is designed to be chamber mounted as shown in Figure 2. There are two versions of this board, a master (2741M -16Y) and a slave (2741-16Y). The master also includes the interface circuits to communicate with the 2748 readout controller. The custom backplane provides the bus and daisy chain wiring to connect up to 16 cards (including 1 master) together to form one readout stream. This backplane also distributes power and the GATE and FAST CLEAR signals to the cards as fast NIM signals. The backplane can be entirely passive, containing termination resistors and connectors, but no ICs or other semiconductor devices.

Figure 1: Model 2741M-16Y developed in conjunction with Yale University.

Figure 2

The Model 2741-16H, shown in Figure 3, is designed to be as small as possible. This 2.125" by 4.5" board utilizes both sides of the board to contain the same number of channels as the 2741-16Y board. There is a slave version only, there is no space on the board for the master interface section. The GATE and FAST CLEAR must be provided as CMOS or TTL instead of NIM. These 2 features, the master section and the NIM-to-CMOS translators must be provided on the backplane. The input and readout connectors are both 36-pin, 0.100" pitch, with different keying (the boards cannot be inserted incorrectly, if the chamber and backplane connectors are properly keyed). This board is intended to be chamber mounted as in Figure 4. The cards must first be plugged into the chamber, then the backplane is plugged on to the cards. This backplane can no longer be passive, it must contain the master interface section, and the NIM-to-CMOS translators for the GATE and FAST CLEAR.

Figure 3: 2741-16H Board developed in conjunction with INFN Sanita.

Figure 4

Model 2741 Preamplifier/Discriminator/Delay/Latch Card

A block diagram of a single channel on either 2741 card is shown in Figure 5. The preamplifier, Model MQS104A, is a high gain transimpedance amplifier, combined with a shaping amplifier. The output pulse shape is optimized for fast proportional chambers. This integrated circuit is implemented as a 4-channel device, in a medium speed bipolar process. The equivalent input noise is less than 3000 electrons, with protection elements and wire capacitance added to the input circuit. The transimpedance gain is 500 kohm, with differential output.

The delay integrated circuit, Model MDL108, combines the discriminator, delay element, coincidence gate and all readout logic in one 8-channel BiCMOS chip. The discriminator threshold is adjustable from 1 V down to below the noise level. The delay element is adjustable from 400 nsec to more than 800 nsec. The delay of any channel can be adjusted to within 2 nsec of the nominal value for the entire system.

Figure 5: Model 2741 Block Diagram

A digital phase-locked loop and voltage controlled delay elements maintain this accuracy from chip to chip and over time and temperature. This phase locked loop is enabled only as required, and does not run continuously. The voltage control is held in a static register.

The coincidence gate can be as short as 30 nsec. The leading edge of the input pulse must be within the gate to produce a latched bit. The readout of the latched data is via a shift register, clocked at 20 MHz. The chip contains all logic required to set up, control, test and read out eight wires. The discriminator thresholds are adjusted in two groups of four channels. There is an enable and a delay trim for each of the eight channels.

All communication to and from the chip is via digital shift registers. A parity bit is added to each group of eight wires during readout, to identify transmission errors. Three eight input OR outputs, a prompt OR, a delayed OR and a latched OR are provided for test and trigger purposes. (These ORs must be used with care! This is a very high gain system.)

There is a chamber connector and a readout/control/power connector. The chamber connector connects directly to the chamber wires. The readout connector plugs into a special backplane (not provided by LeCroy) which supplies power, common signals and the daisy chain wiring to form the shift register. The coincidence gate is distributed (by the experimenter) to this backplane.

System Requirements

The PCOS 4 backplane supplies power and control signals to the 2741 cards.

Since the 2741 cards must plug in to both the proportional chamber and the readout backplane, the backplane must be designed to match exactly the connector spacing of the proportional chamber. For this reason LeCroy does not provide this backplane, but instead provides the complete electrical specifications.

The 2741M-16Y cards incorporate the interface to the 2748 controller module. This card plugs into the master position in the backplane. The 2741-16Y slave cards are daisy-chained together by the wiring pattern on the backplane.

The 2741-16H card uses a similar backplane, but the interface to the 2748 controller is located on the backplane. All 2741-16H cards are slaves. LeCroy will provide the circuit details of the simple interface.

The gate distribution from the experiments trigger to the backplanes is NIM fast and is the OR of the trigger GATE out the TGATE signal from the 2749 system driver. The GATE is routed on the backplane to each 2741 card. This must be designed to minimize the timing skew of the GATE. The TGATE signal is used to calibrate the delay on the 2741 cards.

The fast clear distribution, if required, should be the OR of the experiments fast clear and the TCLEAR signal from the 2749 module.

The readout and control cables are 8 pair cables up to 20 meters long.

Model 2748 Controller

Up to 16 2741-16Y cards are combined to make a readout and control stream of up to 256 wires. One board in 16 also contains the drivers, receivers and connector to communicate to the controller boards, mounted in a nearby rack. An 8 pair cable from each readout string is connected to one of four sections of the Model 2748 CAMAC or VME controller modules. The system block diagram is shown in Figures 6 and 7. Up to 22 2748 cards will fit in a CAMAC crate, up to 21 in a VME crate. One CAMAC crate can control and readout more than 20,000 propor tional chamber wires.

Each 2748 controller card can handle four readout streams, or a total of 1024 wires. To reduce the possibility of noise conducted to the chambers by the readout cables, there are no continuously running clocks between the controller boards and the front end cards. The time to read the data from the chamber-mounted boards to the controller is less than 16 µsec for streams of 256 wires. The formatted data is available for readout over CAMAC

(2748CAM) or VME (2748VME) immediately after all data is read from the chamber boards. The 16-bit data word consists of an eight bit block of adjacent wires, and the address of that wire block (7 bits for 1024 wires). Only blocks of wires containing at least one wire struck are read out. The total readout time depends, of course, on the CAMAC or VME system speed. A fast clear to abort a readout in progress is provided.

The 2748VME offers the functionality of the 2748CAM but in a VME environment. The 2748VME has several major additional features. A 16-event, dual-ported buffer that allows coincident stream readout and 32-bit VME access is provided. There is no significant time penalty for dual ported access. The data words (similar in format to the 2748CAM with the addition of a header word) are stacked into 32 bit words and can be read out to VME (depending on the Master) at rates in excess of 5 MHz (equivalent to 10 MHz 16 bit word rate). This factor of 10 in performance and the multi-buffer operation makes this unit a better choice for experiments with either high occupancies, high rates or both.

Model 2749 Driver

The Model 2749 PCOS driver module, provides precise timing for the delay stabilization, and is the interface to the experiment's trigger system. One 2749 is required for each CAMAC or VME crate. A 10-pin bus connects the 2749 to all the 2748s in the crate, and controls the readout and calibration modes. The gate output from the 2749 is ORed into the experiment's trigger gate and is used for test and calibrate modes.

The 2749VME has almost identical functionality to the 2749CAM but interfaces to the VME bus rather than CAMAC. The only significant difference is the 2749VME enhances the functionality of the 2748VME's support of a multi-event buffer. A Fast Clear Window (FCW) input is provided on the 2749VME. This is distributed to all the 2748VME boards via the command bus.

Figure 6: Typical PCOS 4 System with 2741-16Y cards and CAMAC Readout

Figure 7: Typical PCOS 4 System with 2741-16H cards and VME Readout


Input Sensitivity: 3.5 µV/electron (typical, impulse response).

Impulse Response: 10 nsec rise time, 30 nsec width; linear up to 0.6 V (1,000,000 e-).

Noise Level, Referred to Input: < 3,000 electrons (< 5 nsec impulse, input open circuit).

Comparator Threshold: Adjusts from 0 to 1 V, 6 mV resolution.

Usable Threshold: < 20,000 e-.

Double Hit Resolution: < 80 nsec.

Useful Delay Range: 400 nsec to 800 nsec, programmable in 50 nsec steps (1 nsec resolution with external reference).

Delay Matching, Channel-to-Channel: ±2 nsec, system wide (after user calibration and software programmable trimming).

Delay Stability: ±1 nsec (with periodic calibration).

Built-in Analog Test Pulse: > 100K e- at input. Built-in Diagnostics for System Integrity Prompt, Delayed and Latched OR Outputs for test and trigger use (software enable/disable).

Minimal Cabling: 1 eight pair cable for each 256 wires. On-Chamber Parity Generation and Detection at Con troller During Readout.

Readout Dead Time: < 16 µsec for 256 wire streams.

Compact Data Format: 16-bit includes byte address and 8 bits of wire pattern only for groups containing at least one hit.

Trigger Outputs During Readout: 1 50 nsec NIM pulse for each 8 wire group containing at least 1 hit.

Model 2741-16Y Chamber Mounted Card

There are 2 versions of this card, a master (2741M-16Y) and a slave (2741-16Y). Each stream of up to 16 cards must contain at least one master card. A master card can also be used as a slave.

Size: 4.5" x 10.375"; mount with a .5" pitch minimum.

No. of Channels: 16.

Power Requirements, per 16 Channels: +12 V, ±5% at 0.22 A; +7 V, ±5% at .17 A; -5.2 V, ±5% at 0.14 A.

Negative Input Signal: Diode clamped -0.7 V, 2 V.

Input Impedance: 250 ohm.

Input Connector: 36 contact (2 x 18) PC card edge connector, 0.156" contact spacing.

Readout and Control Connector: 36 contact (2 x 18) PC card edge connector, 0.100" contact spacing.

Master Readout Connector: 16 pin (2 x 18) IDC header with locking ears. Installed only on 2741M-16Y. Con nects only to 2748 stream controller module. Protrudes from board edge by .125".

External Signals Required: GATE, fast NIM, 30 nsec minimum width. FAST CLEAR, fast NIM, 100 nsec minimum width.

Model 2741-16H Chamber Mounted Card

There is no master of this card. All master functions are supplied by the backplane.

Size: 4.5" x 2.125"; mount with a .5" pitch minimum.

No. of Channels: 16.

Power Requirements, per 16 Channels: +12 V, ±5% at 0.2 A; +7 V, ±5% at 0.05 A; -5.2 V, ±5% at 0.04 A.

Negative Input Signal: Diode clamped -0.7 V, 2 V.

Input Impedance: 250 ohm.

Input Connector: 36 contact (2 x 18) PC card edge connector, 0.100" contact spacing.

Readout and Control Connector: 36 contact (2 x 18) PC card edge connector, 0.100" contact spacing.

External Signals Required: GATE, TTL, 30 nsec minimum width. FAST CLEAR, TTL, 100 nsec minimum width.

Model 2748CAM Controller

Single width CAMAC.

Power Requirements: +6 V at 0.4 A; -6 V at 0.2 A.

Stream Cable Inputs: Two 34-pin headers with locking ears. Each header contains 2 16 wire stream cables.

Lemo Outputs: 1 NIM trigger output. During readout, one 50 nsec pulse for each group containing at least one hit.

Command Bus: One 2 x 5 header to be bussed to all 2748s and 2749s.

Model 2749CAM Driver

Single width CAMAC.

Power Requirements: +6 V at 0.4 A; -6 V at 0.2 A.

Lemo Inputs: NIM, 50 ohm. Read, Abort, CAL, Scaler 1, Scaler 2.

Lemo Outputs: NIM, 50 ohm. Busy, Tgate, Tclr, Out3.

Command Bus: One 2 x 5 header to be bussed to all 2748s.

Model 2748VME Controller

Standard B size VME board.

Power Requirements: VME standard supplies; -12 V at < 50 mA, +5 V at < 2 A.

Lemo Outputs: One NIM trigger output. During readout, one 50 nsec pulse for each 8 wire group containing at least one hit. This can be used either for diagnostics or can be directed into an external scaler and counted for contribution to a second level trigger.

Command Bus: One 2 x 8 header to be bussed to all 2748VMEs and the controlling 2749VME. (Note this command bus is not interchangeable with the CAMAC version.)

Model 2749VME Driver

Standard B size VME board.

Power Requirements: VME standard supplies; -12 V at 0.4 A; +5 V at 0.2 A. Note typically only one 2749VME is placed in a crate so its relatively high -12 V draw is not typically a problem with crate selection.

Lemo Inputs: NIM, 50 ohm. Read, Abort, CAL, Scaler, and FCW (Fast Clear Window).

Lemo Outputs: NIM, 50 ohm. Busy, Tgate, Tclr, Out3.

Command Bus: One 2 x 8 header to be bussed to all the 2748VMEs and the controlling 2749VME. (this com mand bus is not interchangeable with the CAMAC version.)

Copyright© September 1995. LeCroy is a registered trademark of LeCroy Corporation. All rights reserved. Information in this publicaction supersedes all earlier versions.