The Summit T416 is Teledyne LeCroy's latest generation of protocol analyzers targeted at high speed PCI Express 4.0 I/O-based applications such as workstation, desktop, graphics, storage, and network card applications.
The Summit T416 analyzer is the computer industry's first high speed PCIe 4.0 protocol analyzer that meets the challenge of 16GT/s and up to x16 lane width protocol analysis. Many PCIe 4.0 product designs are already in progress using the PCIe 4.0 specification. Companies are currently working with the Teledyne LeCroy Summit Z416 protocol exerciser for PCIe 4.0 at the deployment of PCIe 4.0 for host system emulation with their testing needs. This combination of a protocol analyzer and exerciser make Teledyne LeCroy the only supplier of protocol test and development tools for PCIe Gen 4. High speed interposers that provide protocol analyzer connectivity to CEM or other form factor sockets on system boards will still continue to be the principle way to capture PCIe traffic into the protocol analyzer.
PCIe 4.0 technology achieves twice the effective data throughput rate of the PCIe 3.0 standard through a combination of increased data bit rate (8 GT/s moving to 16 GT/s), PCIe 4.0 uses similar encoding as PCIe 3.0 that have proven reliable for data transmission.
With advanced features such as support for PCI Express Spec 4.0, data rates of 2.5, 5, 8 and 16 GT/s, lane widths from x1 to x16, and a full 128 GB of trace memory, the Summit T416 Protocol Analyzer provides unmatched capability and flexibility for developers and users of advanced PCI Express products. The Summit T416 is by far the most advanced and sophisticated PCI Express Analyzer available in the market today.
As with other Teledyne LeCroy PCI Express analyzers, the Summit T416 leverages the intuitive and powerful CATC Trace analysis software system, embedding a deep understanding of the PCI Express protocol hierarchy and intricacies. The colorful, intuitive and easy to use graphical display allows you to quickly capture and validate PCI Express product designs. All Teledyne LeCroy PCI Express protocol analyzers employ high-impedance, non-intrusive probing technology, thereby allowing fully unaltered data pass-through.
In addition to a full suite of advanced hardware and software features, the Summit T416 provides user-convenience and analysis features, such as support for "lane swizzling" which allows a board developer to lay out a Mid-Bus probe pad with lanes in non-standard order, simplifying the design of the board. Internally the Summit T416 maps the lanes back into their correct order and accurately displays the embedded bus traffic. Other software features include enhanced error checking for automatic identification of additional error types, more compact trace files that allow for faster analysis of trace data, and the choice of simplified or advanced modes for setting up trace recording options.
The raw recording mode, Bit Tracer, allows bytes to be recorded as they come across the link, allowing debugging of PHY layer problems and combining the features of a logic analyzer format with a protocol analyzer format. The new auto sense link feature monitors negotiation between devices of different lane widths, and the bifurcated link support recombines multilink PCI Express operations that have been separated into narrower links.
The Summit T416 also supports Ethernet LAN port as a standard feature. By connecting over a LAN, engineers can operate the system remotely (e.g., install the client software on their desktop systems, and control an analyzer operating in a remote lab). Also, multiple engineers working collaboratively can time-share use of a single analyzer, reducing the need for an additional analyzer for each engineer, and increasing the cost effectiveness of the product.
By leveraging years of experience in protocol analysis tools for emerging markets, Teledyne LeCroy's PCI Express protocol analyzers blend sophisticated functionality with practical features to speed the development of PCI Express IP cores, semiconductors, storage, graphics, servers, workstations, bridges, and switches.
| Name | |
|---|---|
PCIe Gen4 OCuLink Host Adapter Quick Start | Product Manual |
PCIe Gen4 OCuLink Interposer Quick Start | Product Manual |
PCIe Gen4 Multi Lead Probe User Manual | Product Manual |
PCIe Gen4 Mid Bus Probe User Manual | Product Manual |
PCIe Gen4 Protocol Analyzer User Manual | Product Manual |
Interposers and probes compatible with the Summit T416
The PCIe 5.0 EDSFF Interposers provides connectivity and monitoring capability for E1.S, E1.L or E3.x type devices targeted at enterprise systems that use the SFF-TA-1002 multi-lane card edge connector. The interposer taps all PCIe protocol traffic between the host and EDSFF device or SSD and records it on the Summit PCIe 5.0 protocol analyzer where protocol issues and performance metrics can be further analyzed and debugged.
The PCIe 5.0 M.2 interposer provides connectivity and monitoring capability for M.2 connector based SSD memory modules targeted at thin client devices such as tablets. The interposer supports 30mm x 22mm, 42mm x 22mm, 60mm x 22mm, 80mm x 22mm , and 110mm x 22mm SSD lengths. This interposer optionally supports the CrossSync PHY technology enabling users to see and correlate both the physical and protocol layers in a unified time aligned view.
The PCIe 5.0 MCIO Cable Interposes provides connectivity and monitoring capability for product designs that incorporate card edge connectors or cabled connector assemblies that utilize the MCIO mechanical connector based on the SFF-TA-1016 specification with PCIe 5.0, NVM Express (NVMe) or Compute Express Link (CXL) technologies.
The PCIe 5.0 Teledyne LeCroy Multi-lead probes allow developers using an embedded PCI Express bus in their PCB designs to tap into the signal traces directly and capture of each serial lane, allowing flexibility to connect to any accessible points on the surface of the PCB.
The PCIe 5.0 OCP NIC 3.0 Interposer allows users to connect a Teledyne LeCroy T4/T5 PCIe(r) protocol analyzer between an OCP NIC 3.0 device and an OCP Server System to monitor, capture, record and analyze protocol traffic. The interposer supports data rates of 2.5 GT/s, 5.0 GT/s, 8.0 GT/s, 16.0 and 32 GT/s, side band signals such as PERST#, WAKE# and SMBus (SMBCLK, SMBDAT). The PCIe 5.0 OCP NIC 3.0 Interposer supports link widths up to x16 and single/multi-hosted configurations.
The PCIe 5.0 U.2/ U.3 (SFF-8639) Interposer is a PCIe Storage Interposer that makes it possible to analyze data traffic from PCIe SSD storage devices to PCIe Storage systems using the U.2/U.3 (SFF-8639) connector. It allows x4 NVM Express, x4SCSI Express or x2 SATA Express host interface based SSD traffic to be monitored, captured and recorded. It supports SRIS, CLCKREQ#, SMBus and Dual port mode when used with MultiPort software option.
The PCIe 4.0 M.2 interposer provides connectivity and monitoring capability for M.2 connector based SSD memory modules targeted at thin client devices such as tablets. The interposer supports 30mm x 22mm, 42mm x 22mm, 60mm x 22mm, 80mm x 22mm , and 110mm x 22mm SSD lengths. This interposer optionally supports the CrossSync PHY technology enabling users to see and correlate both the physical and protocol layers in a unified time aligned view.
A mid-bus probe is a means of connecting a protocol analyzer to an embedded PCI Express bus (e.g., a bus which runs between chips on the same circuit board). In order to use a mid-bus probe, an industry-standard connector pad is designed into the board to allow access to the bus signals. These connector pads are designed according to specifications provided by the PCI-SIG®
The Multi-lead Probe is a specialty probe that makes it possible to analyze PCI Express serial data traffic in an embedded data bus (e.g.., a PCI Express bus that runs between components on the same PCB). As long as the traces are exposed on the surface of the PCB, the Multi-lead Probe allows for attachment to isolation resistors soldered to the bus traces and provides a data capture path for a Teledyne LeCroy PCI Express protocol analyzer. This eliminates the need to design any special purpose footprints or connectors into the board.