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Insight into the standard based on our real world testing experience
Instruction from experts with over 20 years of experience in storage
and networking
Introduction to PCIe®
An introduction to PCIe as a protocol as well as the specifications
and organization that govern it. Also deals with the marketing aspects that drive
PCIe in the current product landscape by addressing the following questions:
- What is PCIe?
- Why do we need PCIe?
- What is the governing organization for PCIe?
- What are the relevant specifications for PCIe and where can they be found?
Components and Terminology
A discussion of concepts, terms, and devices that are integral to
the understanding and functionality of PCIe. Students will be given a vocabulary
to effectively communicate ideas throughout the learning process by exploring
such concepts as:
- Differential Signaling
- Lanes vs. Links
- PAM-4, FEC, and Flit Mode
- Scrambling and Encoding
- Switches and Bridges
PCIe Architecture
An examination of the PCIe protocol, its layering, and
functionality. This section contains the framework on which the details of the
other sections will rest. It covers basic layout of a PCIe system as well as such
topics as:
- PCIe Topology
- Generations and Speeds
- Connectors and Form Factors
- Layering and Functionality
Flit Mode
A discussion about the changes made to PCIe in version 6, its
signaling, error correction and manifold protocol changes made to accommodate the
new speed and signal strength inherent in PCIe Gen6. These changes have made a
big difference in how PCIe signaling takes place.
- Prefixes are rethought
- Flow Control optimizations
- Selective replay in ACK-NAK
- Multiple TLPs in single transaction
- DLLP return slot guaranteed
PCIe ACK/NAK and Flow Control
This section deals with the functions of reliability and overflow
prevention by discussing such subjects as:
- ACK/NAK
- TLP Sequencing and Buffers
- Scaled, Shared, Merged and Infinite Flow control
- Selective and Bulk replay
PCIe Configuration and Enumeration
A step-by-step look at the PCIe configuration and enumeration
process that discusses the following items:
- PCIe Configuration Space
- Base Address Registers (BAR)
- Bus Enumeration
Major ECNs Since 5.0 Release
There have been a few big ECNs that have come out since the release
of 5.0. These are detailed here, as they do have bearing on several aspects of
6.0.
- ATS 1.2
- Big Power
- Unordered IO
Analyzer Operation and Configuration
Reflect on each PCIe topic with a guided walk-through lab of the
best practices for analyzer configuration and trace analysis.
- 5+ Labs with traces
- How to setup for capture
- What to capture
- How to effectively trigger for capture
- How to debug and insert errors