PCIe Boot Camp Class - Austin Labs Testing and Training

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Flexible delivery options designed to fit your team’s schedule, scale, and learning style.

Online Training

Online Training

Self-paced modules built for engineers who want to learn on their own schedule. Includes videos, text explanations, interactive checkpoints, and hands-on exercises. All based on the same course material used in our live sessions.
    Private Training

    Private Training

    A dedicated instructor-led session for organizations that want to train multiple engineers at once. Your team gets direct access to an expert, tailored pacing, and the ability to ask questions specific to your environment or use cases.
      Public Training

      Public Training

      Quarterly live sessions open to individual engineers or small groups. Join a scheduled class, learn alongside peers from across the industry, and get real-time instruction using the same core course content.

        Overview

        Course Outline

        What to Expect

        Analyzer Operation and Configuration

        Austin Labs Testing Services

        Overview

        Get concrete, detailed answers to your questions:

        • Why is PCIe 6.0 so different?
        • What are Flits and why are they needed?
        • What has changed from previous versions of PCIe?
        • How does PCIe initialize a link?
        • How are QoS and Flow Control different in PCIe 6.0?
        • How does a link negotiate to 64GT/s?
        • What are the noise characteristics of PAM4?

        Learn these things and more in Austin Labs PCIe 6.0 Boot Camp training. Based on the latest PCIe specifications as well as real world test findings from Austin Labs Testing Services, this training covers the PCIe protocol specifically for those with little time who need to understand the basic changes from a high level.

        This class is designed for engineering-minded individuals such as test leads, program managers, design engineers, technical/product field support, and storage/system administrators who need the basics behind the 6.0 changes.

        Lab time included in every class. Outlines are fully customizable for private classes!

        Course Outline

        • PAM4 and Forward Error Correction (FEC)
        • Flit Mode
        • Shared credits
        • Selective Replay
        • ATS 1.2 changes
        • Unordered IO
        • Deferrable Memory Writes
        • Segments and Peer to Peer Flit routing
        • Deprecations
        • Major ECNs added
        • Analyzer Operation in Flit Mode

        What to Expect

        Never pay extra to look at trace captures

        Insight into the standard based on our real world testing experience

        Instruction from experts with over 20 years of experience in storage and networking

        PAM4 and Forward Error Connection

        As the transfer rates keep going up, PCI-SIG has found new and innovative ways to make the connections reliable. This section details the basics of this major speed increase and how such simple changes ripple through the architecture.

        • The basic encoding of PAM4
        • What this means for noise margins
        • Forward Error Correction
        • Major changes in basic signaling means a complete redesign of the entire protocol
        Flit Mode

        The PCI-SIG was given the chance to completely redesign the protocol used because of the changes brought by PAM4. Flit mode allows that to happen. Many transactions are up to 80% more efficient now.

        • Prefixes are rethought
        • Flow Control optimizations
        • Selective replay in ACK-NAK
        • Multiple TLPs in single transaction
        • DLLP return slot guaranteed
        Shared Credits

        Rethinking flow control allows a more optimized use of buffer memory, which can now be shared across VCs and TLP types.

        • Fixed Credits
        • Shared Credits
        • Optimized flow control packet
        • Layering and Functionality
        Selective Replay

        This change offers increased replay efficiency in noisy environments. This is been one item that has been talked about for years, but could not be done until 6.0 because of the huge impact this small change has on the whole protocol design.

        Deferrable Memory Writes

        This section is about some new features added to support other fabric types. There are new remote system type fabrics that have asked for such features that we will see in the future. These are the beginnings of those architectural changes.

        Deprecations

        When a major redesign like this comes along, we have the opportunity to remove outdated ideas, too. This section covers those items.

        Major ECNs Since 5.0 Release

        There have been a few big ECNs that have come out since the release of 5.0. These are detailed here, as they do have bearing on several aspects of 6.0.

        • ATS 1.2
        • Big Power
        • Unordered IO

        Analyzer Operation and Configuration

        Each course features multiple hands on labs that immerse you in the same PCIe analyzer software used by industry professionals to break down and interpret real world traces. You’ll work directly with specialized trace files that we provide, and together we’ll walk through the process of efficiently collecting data, identifying key events, and debugging complex scenarios. These labs are designed to give you practical experience, not just theory, so you’ll leave with the confidence to apply what you’ve learned in real environments.

        In these labs, you will:

        • Analyze PCIe flit mode boot traces and configuration traces to understand system initialization and protocol behavior.
        • Develop a systematic approach to debugging traces, learning what patterns, anomalies, and error conditions to look for.
        • Gain hands on familiarity with analyzer workflows, so you can replicate the process when working with your own hardware and systems.

        Austin Labs Testing Services

        We test customers’ products quickly and thoroughly in an enterprise environment to ensure that products will survive the rigorous demands of mission-critical applications. Customers come to us for our fast turnaround, superior analysis, excellent results, competitive prices, and, of course, 100% confidentiality. We work hand-in-hand with our customers’ engineers to provide solutions, not just information. We provide not only the results of our tests, but also the debug, analysis, and regression testing that is needed to ensure that the products we test perform as expected—not for our customers, but for your customers.

        About Austin Labs

        Austin Labs is the industry leading third-party testing and training facility. With state-of-the-art test facilities located around the world and industry expertise Austin Labs takes advantage of the wide array of Teledyne LeCroy tools for validation testing of products from server/storage to client systems with expertise in PCIe, NVMe, CXL, Ethernet, Fibre Channel, SAS, SATA, USB, Thunderbolt, Bluetooth, WiFi, HDMI, DisplayPort, MiPi C/D-Phy, MiPi M-Phy, and many others.

        Our engineers helped develop some of the industry’s key technologies and continue to have a vigorous passion for improving products and sharing their knowledge. This experience and enthusiasm translates into the highest quality testing and training services possible.

        For more information please contact:

        [email protected]

        Have a Question or Want to Schedule a Class?

        We’re here to help and answer any question you might have. We look forward to hearing from you