Summit T34 Analyzer
The Summit T34 Protocol Analyzer captures, decodes and displays PCIe 3.0 protocol traffic data rates for x1, x2, x4 lane widths.
Summit T34 Analyzer
Request a QuoteKey Features
- Find errors fast
- One button error check
- Fast upload speed
- Large trace memory
- Powerful triggering/filtering
- See and understand the traffic
- Get useful information
- More choices of data views
- More ways to analyze data
- Probing
- Gen3 PCIe Slot Interposer
- Custom form-factors
- SFF-8639 Interposers
- M.2 Interposer
- Mid-bus probe
- Multi-lead solder-down probe
- Additional probes available
- Accurate data capture
- 100% data capture in a small, portable unit (only 3 lbs)
- Supports data rates up to 8 GT/s (PCIe® 3.0)
- Captures up to four lanes of data traffic (expandable to 8 lanes with 2 units)
- Provides support for CLKREQ# for L1 substate testing
- Supports SRIS
- 4 GB trace memory is standard, expandable up to 32 GB (64 GB with two units)
Portable and Compact
The Summit T34's small dimensions (209 x 40 x302 mm) and at a light weight of 3 lbs it is clearly the most portable compact PCI Express protocol analyzer in the market today.
Powerful Views
As with other Teledyne LeCroy PCI Express analyzers, the Summit T34 leverages the intuitive and powerful CATC Trace analysis software system, embedding a deep understanding of the PCI Express protocol hierarchy and intricacies. The colorful, intuitive and easy to use graphical display allows you to quickly capture and validate PCI Express product designs. The application display is highly configurable and can be modified to fit most users debugging styles. A customizable multi-state trigger makes it easy to discover protocol issues on the bus. Features such as multiple local/global timers and counters allow the user advanced control to create sophisticated trigger sequences.
PCI Express Storage
The portable Summit T34 protocol analyzer is designed to support multiple PCIe storage protocols such as SATA Express, NVMe and SCSI Express. The new storage related capabilities and new protocol analysis views optimized for PCIe storage development are currently supported across the product line and make these tools valuable to understanding data transmission from the PCI Express protocol layer up to the command layer.
Lane Swizzling
In addition to a full suite of advanced hardware and software features, the Summit T34 provides user-convenience and analysis features, such as support for "lane swizzling" which allows a board developer to lay out a Mid-Bus probe pad with lanes in non-standard order, simplifying the design of the board. Internally the Summit T34 maps the lanes back into their correct order and accurately displays the embedded bus traffic. Other software features include enhanced error checking for automatic identification of additional error types, more compact trace files that allow for faster analysis of trace data, and the choice of simplified or advanced modes for setting up trace recording options.
Bit Tracer
A new raw recording mode, Bit Tracer, allows bytes to be recorded as they come across the link, allowing debugging of PHY layer problems and combining the features of a logic analyzer format with a protocol analyzer format. The new auto sense link feature monitors negotiation between devices of different lane widths, and the bifurcated link support recombines multilink PCI Express operations that have been separated into narrower links.
Lan Support
The Summit T34 also supports Ethernet LAN port as a standard feature. By connecting over a LAN, engineers can operate the system remotely (e.g., install the client software on their desktop systems, and control an analyzer operating in a remote lab). Also, multiple engineers working collaboratively can time-share use of a single analyzer, reducing the need for an additional analyzer for each engineer, and increasing the cost effectiveness of the product.
Flexible Configurations
The Summit T34 is available in two configurations—that support either x1, x2, and x4,; or x1, x2, x4, and x8, if combined with a second Summit T34—to match user requirements with available budgets.
Debug in any PCIe environment
By leveraging years of experience in protocol analysis tools for emerging markets, Teledyne LeCroy's PCI Express protocol analyzers blend sophisticated functionality with practical features to speed the development of PCI Express IP cores, semiconductors, graphics, servers, workstations, bridges, and switches.
Resources
| Name | |
|---|---|
Summit T34 Analyzer Datasheet | Datasheet |
NVMe Datasheet | Datasheet |
PCIe Suite Data Pattern Trigger Teledyne LeCroy PCIe suite supports a versatile data pattern trigger. This technical brief will show how us the trigger in typical use cases as a tool to locate a file or directory access or simply to trigger on a starting LBA. This technical brief will focus on an NVMe application however the methodology is applicable to many other scenarios. | Application Note |
PCIe Suite Data Pattern Search Teledyne LeCroy PCIe suite supports a versatile data pattern search. This technical brief will show how us the search tool to locate a file directory to determine the starting LBA of the directory structure. | Application Note |
Capture of an NVMe Boot up trace In order for the LeCroy Summit Protocol analyzer to properly decode and display traces for NVMe, the analyzer software must have record of which PCIe devices are Mass Storage, what is the MBAR address, what address each queue has, as well as several other pieces of information that is typically established shortly after a PCIe link is established and devices under test come online. Typically the easiest way for the analyzer to get this information, and properly decode an NVMe trace, is to capture a trace at boot up. Every trace captured after this boot up trace will used the same decoding mapping, eliminating the need for future boot up captures. While this is a simple process, there are a few settings that may help get the complete trace with all relevant details needed for the SSD decode mapping. | Application Note |
NVMe Protocol Analysis Features for Storage Development and Test
| Name | |
|---|---|
PCIe Gen3 Summit T34 Protocol Analyzer Quick Start | Product Manual |
Interposers and Probes
Interposers and probes compatible with the Summit T34
PCI Express 4.0 - M.2 Interposer
The PCIe 5.0 M.2 interposer provides connectivity and monitoring capability for M.2 connector based SSD memory modules targeted at thin client devices such as tablets. The interposer supports 30mm x 22mm, 42mm x 22mm, 60mm x 22mm, 80mm x 22mm , and 110mm x 22mm SSD lengths. This interposer optionally supports the CrossSync PHY technology enabling users to see and correlate both the physical and protocol layers in a unified time aligned view.
PCI Express 3.0 - CEM Interposer
The Teledyne LeCroy Gen3 Interposer with CLKREQ# and SRIS support provides a simple and easy-to-use way to probe PCI Express traffic between a host and PCIe® expansion card. The interposer assures reliable data transmission while providing 100% capture of all data traffic flowing through the PCIe slot interface.
PCI Express 3.0 - M.2 Interposer
The M.2 interposer provides connectivity and monitoring capability for M.2 connector based SSD memory modules targeted at thin client devices such as tablets. The interposer supports 42mm x 22mm, 60mm x 22mm, 80mm x 22mm , and 110mm x 22mm SSD lengths.
PCI Express 3.0 - MidBus Probe
A mid-bus probe is a means of connecting a protocol analyzer to an embedded PCI Express bus (e.g., a bus which runs between chips on the same circuit board). In order to use a mid-bus probe, an industry-standard connector pad is designed into the board to allow access to the bus signals. These connector pads are designed according to specifications provided by the PCI-SIG®
PCI Express 3.0 - Multi-lead Probe
The PCIe 3.0 Teledyne LeCroy Multi-lead probes allow developers using an embedded PCI Express bus in their PCB designs to tap into the signal traces directly and capture of each serial lane, allowing flexibility to connect to any accessible points on the surface of the PCB.
PCI Express 3.0 - U.2 Dual Port Interposers
The Dual Port -inch or 12-inch PCIe 3.0 U.2 (SFF-8639) Interposer is a PCIe Storage Interposer that makes it possible to analyze data traffic from PCIe SSD storage devices to PCIe Storage systems using the U.2 (SFF-8639) connector. The interposer when used with a dual PCI Express protocol analyzer setup allows traffic from dual port NVM Express and SCSI Express SSD drives to be monitored, captured and recorded from each port simultaneously. The Interposer supports SRIS, CLCKREQ# and SMBus.
PCI Express 3.0 - U.2 Standard Interposers
The Standard Port 5-Inch or 12-inch PCIe 3.0 U.2 (SFF-8639) Interposer is a PCIe Storage Interposer that makes it possible to analyze data traffic from PCIe SSD storage devices to PCIe Storage systems using the U.2 (SFF-8639) connector. The interposer allows x4 NVM Express, x4SCSI Express or x2 SATA Express host interface based SSD traffic to be monitored, captured and recorded. The Interposer supports SRIS, CLCKREQ# and SMBus.
PCI Express 2.0 - VPX Interposer
The Teledyne LeCroy Specialty Interposer Card for VPX Applications supports VPX developers by providing a quick and easy way to connect a Teledyne LeCroy protocol analyzer to the PCI Express data channels in the VPX interface. The protocol analyzer can then capture, decode and display all PCI Express data traffic between the VPX expansion card and the VPX backplane. The VPX Interposer Card supports PCI Express data channels with lane widths up to x8, at PCIe® 2.0 (Gen2) data rates up to 5 GT/s.
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