The Voyager M4120 equips engineers with the clearest and most comprehensive views of USB4 120Gb/s Asymmetric Link protocol, accelerating validation and getting products to market faster.
Capture / Analyze USB4 & USB 3.2 including PD (EPR up to 50V) and SBU traffic to see end-to-end host, hub, and device operation.
The front-end of the Voyager analyzer features USB4 certified connectors that support the full 80Gb/s data rate for loss-less capture of traffic from all active links.
The Voyager series remains the top protocol analysis choice for engineering teams. The M4120 adds full USB4 V2 power with Gen 4 120Gb/s Asymmetric Link rates to the arsenal without compromising on legacy speeds. Testing of USB4 Gen 3x2 (40Gb/s), USB 3.2 Gen 2x2 (20Gb/s), Gen 2x1 (10Gb/s), and USB 2.0 speeds are also fully supported, as well as Power Delivery (EPR up to 50V).
The Voyager M4120 highlights protocol violations at every layer— from CRC errors to framing and timing faults. Errors are flagged and annotated directly in the trace, giving you immediate insight into why a link failed and what needs to be corrected.
The Voyager M4120 Power Tracker option monitors and displays vBus power and current graphically in a time-line format. The voltages are synchronized to trace events allowing users to verify power state transitions at the protocol and electrical layers. Separate power graphs are provided for CC and VCONN making it easy to debug logical Type-C state transitions.
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Voyager M4120 Datasheet | Datasheet |
Get on the fast-track with an insightful review of USB4 80Gb/s & Thunderbolt™ 5. This time-saving introduction will provide a concise review of the changes in the USB4 80Gb/s protocol.
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USB Protocol Suite User Manual | Product Manual |
Unlock full-rate USB4 v2 analysis with the Asymmetric Mode option for the Voyager M4120. This option enables capture and analysis of USB4 Asymmetric Link configurations, allowing one link partner to transmit at up to 120?Gb/s using three lanes. With Asymmetric Mode enabled, engineers gain clear visibility into asymmetric traffic behavior, making it possible to validate and debug products that rely on asymmetric operation to achieve maximum performance.
The exerciser adds a flexible traffic generation capability for USB4 80Gb/s and Thunderbolt™ 5 to the Voyager M480x platform. It allows users to transmit custom packets over standard USB Type-C cables with low-level control of headers, payloads, timing, and link states. Seamlessly integrated with the protocol analyzer, the M480x exerciser can emulate host or device router operations while recording the real response from the DUT. Leveraging the same proven architecture developed for SuperSpeed USB, the M480x exerciser adds Gen 4x2, Gen3x2 and Gen2x2 support allowing users to perform initial power-on, functional and compliance testing for next generation USB4-V2 chipsets.
The Voyager Power Tracker option monitors Vbus, CC and VCONN voltage/current and displays power levels graphically in a time line format. This power information is synchronized to the trace allowing users to verify power state transitions at the protocol and electrical layers. The Power Tracker continually samples voltage during normal operations. It includes markers and delta measurements with point and click ease. Required for running PD Compliance Suite, the Power Tracker is invaluable for validating VBUS, PD, Type-C and Vconn behaviors.
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SimPASS USB brings the powerful Teledyne LeCroy data traffic analysis capabilities commonly used for post-silicon testing to the simulation environment. Users of cutting edge simulation tools can now export and view test vectors directly in the Teledyne LeCroy USB trace viewer.
SimPASS USB now supports USB4 40Gb/s and 80Gb/s simulation files. This allows vendors to generate RTL vector files (that describe USB I/O traffic in the pre-silicon phase) and then display and analyze these exchanges in the same way as hardware-derived trace files in the post-silicon phase. Viewing simulation files that illustrate potential flaws in data and transaction packets from the I/O stream, SimPASS enables developers to more completely test and debug the logic design before committing the design to silicon. Issues such as flaws in power state transitions, improper credit flow exchanges and marginal timing handshakes can be discovered, tracked to their source, and resolved, resulting in faster time-to-market and lower development costs for SoCs. During any redesign cycle, fixes for bugs (identified in the previous cycle) can be verified by re-testing the fixes during simulation using the SimPASS software.
The Teledyne LeCroy Gen T Exerciser option enables comprehensive functional and compliance testing, helping ensure reliable operation and faster performance for next-generation USB4 Gen T hosts and devices. When combined with the Voyager M4x or M480x Exerciser system, the Gen T option provides precise control of Gen T protocol transactions. This option is a requirement to gain access to the Gen T Compliance tests, which will be added in an upcoming USB4-CV tool from the USB Implementers Forum (USB-IF). There are currently 20 test cases fully aligned with the latest USB-IF specifications and designed to validate Gen T device enumeration, functionality and error recovery. Part#: USB-AC60-V08-A.
