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Teledyne LeCroy’s QPHY-DDR4 automated compliance software enables engineers to consistently test DDR4 and LPDDR4/4X memory standards set by the JEDEC specification. This 4th generation of memory provides nearly double the transfer speeds of previous ranges and lower operating voltages. QualiPHY automated compliance software has a complete set of Clock, Electrical, and Timing tests outlined by the JEDEC. Paired with the DDR Debug Toolkit provides the tools to confidently test all stages of memory design, from initial turn-on through final compliance test

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Key Features
  • DDR4 test coverage as described by JESD79-4D
  • LPDDR4 & LPDDR4X test coverage as described by JESD209-4D, JESD209-4-1A
  • Test speeds up to 4200 MT/s
  • Perform automated compliance of JEDEC electrical requirements
  • Measurement repeatability, consistency and accuracy
  • Save Pass/Fail reports with annotated screenshots
  • Analyze compliance failures in a dedicated Debug Toolkit
  • Included in DDR5 Software Bundle

Clock Tests

The DDR4 specification requires clock jitter to be separated into random and deterministic components, which is a first for DDR specifications. QPHY-DDR4 leverages industry leading serial data algorithms to perform the jitter breakdown for tJIT(per). In addition to these tests, QPHY-DDR4 will test average clock period, absolute clock period, average high/low pulse width, absolute high/low pulse width, cycle-cycle jitter, duty cycle jitter, and cumulative error over n period tests.

Timing Tests

tDQSQ verifies the skew between DQS and the associated DQ within a read burst. QPHY-DDR4 will perform this measurement on every DQ transition within a read burst. Upon completion each test will display a fully annotated "worst case measurement" screenshot which includes trace labels for the signals under test and relevant voltage levels.

Electrical Tests

The differential and single-ended slew rates defined by the JEDEC standards for DDR4/LPDDR4/4X measure every rising and falling edge within a write burst. QPHY-DDR4 will measure every transition within each write burst in the acquisition providing large statistically results in a short period of time. In this picture over 3,000 slew rate measurements were performed which ensures that the true maximum and minimum points have been caught without requiring multiple acquisitions.

DDR5 Software Bundle

The best tools cover all stages of design, from early turn-on through compliance. This means planning for the future, it might be testing DDR3 to DDR4 or upgrading to DDR5 designs. The DDR5 Bundle includes all the best tools (DDR Debug Toolkit + QualiPHY) across all generations, in a single purchasable software bundle.

QualiPHY is designed to reduce the time, effort, and specialized knowledge needed to perform compliance testing on high-speed serial buses.
  • Guides the user through each test setup
  • Performs each measurement in accordance with the relevant test procedure
  • Compares each measured value with the applicable specification limits
  • Fully documents all results
  • QualiPHY helps the user perform testing the right way—every time!
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