DDR and LPDDR Memory Compliance Testing and Debug
Establishing basic operation, signal checks and validating responses is foundational during board turn-ons. This means knowing if signals look correct, if the signals are communicating, if the command bus is operational, are voltage and timing settings in the right magnitude of error, do channels show both Read and Write packets. These early steps are critical and require simple, dedicated tools built just for this phase of memory design. This isn’t compliance, it’s more than that.
- Do the signals out of the DRAM (Read) or Controller (Write) look correct?
- Are initial voltage and timings details in the right locations?
- Is the command bus communicating correctly?
Minimizing probe and interposer impacts on your design is critical to maximize DDR signal quality into your oscilloscope. Teledyne LeCroy DH Series Probes are low-noise & low loading active probes with solder-in tips and QuickLink adapters. An interposer can further enhance signal quality by locating the test point close to the ball of the DRAM. Then, the probe and interposer combination can be de-embedded with Virtual Probe.
JEDEC requires DDR measurements be performed at the ball of the DRAM (the BGA), or test location #1 in the image. If your probe location is currently at #2 (interposer) or #3 (mid-bus or at a VIA) the probe location can be moved virtually before beginning DDR validation or measurements.
- De-embedding .2SP, .3SP and .6SP S-parameter files accounts for T-points with interposers and risers.
- Virtual Probing can move the probe point to the memory controller to analyze stressed Read packets.
- Remove issues caused by mid-bus probe locations
Probing setup errors, such as reflections, can be confused with DDR design quality. Teledyne LeCroy’s Virtual Probe @ Receiver can be used to eliminate reflections and give you a better picture of your actual DDR design performance.
- Remove termination problems with Virtual Probe at the receiver (VP@RCVR).
Teledyne LeCroy's HDA125 Logic Analyzer probes DDR command addresses digitally and conserves analog oscilloscope channels for other signals. DDR protocol decode and trigger can be used on these digitally probed signals to isolate DDR activities and data signals for faster debug. The HDA125 Logic Analyzer supports the highest 8400 MT/s DDR5 CMD address lines for decode and triggering.
- Industries only Decode & Trigger up to DDR5
- Decode JEDEC's Command Truth Table
- Perform better R/W separation, the command bus knows the packet locations
- Overlay R/W Visuals on Channels
DDR memory operation stability is optimized when voltages, timing and packet parameters are adjusted to their fullest potential in your design. Teledyne LeCroy’s DDR Debug Toolkits help you better understand DDR operation and improve your DDR testing.
Multiple Scenario Viewing
- Layout 4 unique testing situations
- Before vs. after signal comparisons
- De-Embedding vs. Original
- Read and Write Strobe-Clock Compares
- Measurement Comparisons
Eye Diagram, Mask Testing & JEDEC Specific Measurements
- Interactive user Toolkit
- Eye Diagram & Mask Testing
- JEDEC or custom masks
- “Failures” on mask analysis
- DDR Specific Measurements
Highest R/W Accuracy
- Decode the command address
- Know exactly where R & W occur
- Upgradable external logic analyzer
- Lowest capacitance loading
(6x lower than competitors)
Read More
Reduce Inconsistencies
- Same setup, every time
- Save & recall configurations
- Connection diagrams
- Analyze failures in Debug Toolkit
The Latest JEDEC Requirements
Full automation coverage of JEDEC.
- Fast automated test coverage
- Complete testing at DRAM BGA
- Measure CLK, DQS, DQ, CA signals
Save Reports
Quickly save your work at all stages of your testing and design journey.
- Pass or fail measurement results
- Save HTML or PDF reports
- Screen images with annotations
September 2023 Updates and Additions
- Easier UI Work-flow improvements for DDR Toolkit
- New CMD Bus and Decode tab
- New Protocol/Mask Selection, Autoset, R/W Separation
- Added LPDDR4X Support & Mask Testing
- Added WavePro HD support for LPDDR4/4X Debug Toolkit
- Added QualiPHY Compliance Testing for LPDDR4X
- Added QualiPHY DDR5 BETA Testing
| Document Name |
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| DDR5 Datasheet
QualiPHY DDR5 System Level Preliminary Datasheet is currently available on the Light House Partners page. Users interested in Beta testing can sign up, get approved and start testing.
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Explore More
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| DDR4/LPDDR4/LPDDR4X Datasheet
QualiPHY (QPHY-DDR4) Datasheet outlines testing capabilities, ordering information and more for engineers interested in memory design.
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Datasheet
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| DDR3/DDR3L/LPDDR3 Datasheet
QualiPHY (QPHY-DDR3) Datasheet outlines testing capabilities, ordering information and more for engineers interested in memory design.
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Datasheet
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| DDR & LPDDR Debugging Toolkit Datasheet
DDR Debug supported all stages of design for DDR 2/3/4/5 and LPDDR2/3/4/4X and allows for deep troubleshooting.
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Datasheet
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| DDR2 Datasheet
QualiPHY (QPHY-DDR2) Datasheet outlines testing capabilities, ordering information and more for engineers interested in memory design.
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Datasheet
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| LPDDR2 Datasheet
QualiPHY (QPHY-LPDDR2) Datasheet outlines testing capabilities, ordering information and more for engineers interested in memory design.
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Datasheet
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DDR5 Memory Test and Read-Write Separation
Become and Expert in DDR Memory Physical Layer Testing for DDR Debug, Compliance and Validation
Join Teledyne LeCroy for this masterclass webinar series to learn about the basics of DDR testing with oscilloscopes, including common test preparation and challenges, the difference between compliance and debug test tools, and practical tips and techniques to increase your DDR validation efficiency and apply the correct debug tools.
Register for all
Part 1 Fundamentals of DDR Memory Physical Layer Testing
In this session, we will provide an overview of DDR interfaces and test challenges. Special attention will be paid to the differences between validation and compliance test requirements, and probing for optimum effectiveness.
Part 2 Beyond DDR Compliance Testing — Using Advanced Debug Tools
In this session we review the latest DDR test requirements and provide practical advice on solving test challenges. We will provide guidance on how to test to the latest JEDEC standards and proper use of debug tools to overcome test and validation challenges.
Part 3 Top Tips and Techniques for Better DDR Probing and Testing
In this session we get specific on how to address real-world probing and connectivity issues that impact DDR3/LPDDR3 and DDR4/LPDDR4 measurement capabilities. We will provide examples of what to do or not do and a pre-compliance test checklist will be reviewed.
Part 4 DDR Debug Scenarios and Virtual Probing
In this session we demonstrate the utility of DDR eye patterns required for testing and debugging DDR3/LPDDR3 and higher speed DDR4/LPDDR4 signals using real-world DDR debug examples and specialized connectivity examples.
DDR4/LPDDR4/LPDDR4X Instruction Manual
QualiPHY (QPHY-DDR4) Instruction Manual for step-by-step instruction on how to operate and test the DDR4, LPDDR4, LPDDR4X DRAM standards.
DDR3/DDR3L/LPDDR3 Instruction Manual
QualiPHY (QPHY-DDR3) Instruction Manual for step-by-step instruction on how to operate and test the DDR3, DDR3L, LPDDR3 DRAM standards.
DDR & LPDDR Debugging Toolkit Instruction Manual
DDR Debug supported all DDR 2/3/4/5 and LPDDR2/3/4/4X/5 and allows for troubleshooting tough problems. This manual helps you use the tool to it’s full potential
DDR2 Instruction Manual
QualiPHY (QPHY-DDR2) Instruction Manual for step-by-step instruction on how to operate and test the DDR2 DRAM standard.
LPDDR2 Instruction Manual
QualiPHY (QPHY-LPDDR2) Instruction Manual for step-by-step instruction on how to operate and test the LPDDR2 DRAM standard.