The QualiPHY SATA software option for LeCroy oscilloscopes provides an extensive set of validation/verification and debug tools written in accordance with SATA Gen1 (1.5 Gb/s), SATA Gen2 (3.0 Gb/s) and SATA Gen3 (6.0 Gb/s) electrical specification. QPHY-SATA covers the interoperability tests defined by the SATA-IO including all the PHY General Requirements (PHY), PHY Transmitted Signal Requirements (TSG), and PHY OOB Requirements (OOB) for internal SATA products as well as eSATA products. These capabilities make QPHY-SATA an all-inclusive automated test suite that meets the requirements for Gen1 (1.5 Gb/s), Gen2 (3.0 Gb/s) and Gen3 (6.0 Gb/s) Serial ATA trans mitter compliance testing.

• QPHY-SATA provides a highly automated and easy-to-use solution for Serial ATA Gen1 (1.5 Gb/s), Gen2 (3.0 Gb/s) and Gen3 (6.0 Gb/s) compliance testing
• Bandwidths and sample rates suited to the data and edge rates of today's highest speed devices
• Long memory to capture low-speed phenomena such as Spread Spectrum Clocks (SSC) embedded in high-speed data
• Powerful and flexible analysis tools offer unmatched insight for diagnosing and solving elusive problems
• Fast processing throughput maintains interactive operation even while performing complex calculations on long waveforms

QPHY-SATA provides a highly automated and easy-to-use solution for Serial ATA Gen1 (1.5 Gb/s), Gen2 (3.0 Gb/s) and Gen3 (6.0 Gb/s) compliance testing in accordance with SATA-IO Logo requirements.

The use of Spread Spectrum Clocking (SSC) in transmitted signals is an optional feature of the SATA specification. When SSC is enabled, measurements such as frequency modulation rate and deviation must also be verified per the specification. The QPHY-SATA software works in conjunction with the deep memory and powerful analysis library of the SDA instrument family to greatly simplify this verification process. Clock recovery circuitry and clock extraction via Phase-Locked Loops (PLLs) is another significant design consideration. Flexible clock recovery options in the SDA allow for the replication of virtually any real receiver PLL configuration, enabling the simulation of "what if" scenarios. Jitter results can be measured exactly as the receiver would see them.

Spread Spectrum Clock (SSC) validation requires long memory and specialized analysis functions. LeCroy is the only manufacturer that can precisely track SSC profiles through multiple cycles in real-time.

Measurement results often need to be summarized and tabulated to quickly verify specifications. This information, together with instrument and signal acquisition/test condition setups, results in a fully documented record. QPHY-SATA streamlines this process by incorporating an automatic HTML report generation engine. The created test reports contain tabulated numerical values for each individual test result, including PASS/FAIL and specification limit columns. Reports can also be saved as PDF, HTML or XML.

OOB Timing Measures COMINIT/COMRESET and COMWAKE bit rate, burst and gap widths.

Since its introduction, the SDA has been viewed as a high-performance signal integrity instrument due to its bandwidth, sampling rate, memory depth, and processing capability. LeCroy's instrument family adds the ability to measure jitter and eye patterns in real time. The QPHY-SATA package takes this capability one step further with the inclusion of the Advanced Serial Data Analysis Library. This feature provides ultimate control of PLL design, jitter measurement conditions including detailed Data Dependent Jitter (DDj) breakdown and bit error rate (BER) analysis. The SDA provides pinpoint accuracy for eye mask violation locator, even in the presence of SSC. While the SATA specification does not require eye patterns as part of its measurements, QPHY-SATA users have a choice of implementing integrated mask testing featuring an eye mask violation locator.

Clock-to-data Jitter Measurements. Clock recovery options enable you to meet the Jitter Transfer Function (JTF) specification requirements. Industry-leading Q-Scale analysis provides the industry's most precise breakdown of Random and Deterministic Jitter (Rj and Dj).

Connection Diagrams prompt the user to set the DUT to output specific test patterns.

Compliance Reports contain all of the tested values, the specific test limits and screen captures. Compliance Reports can be created as HTML, PDF or XML.

QualiPHY is designed to reduce the time, effort and specialized knowledge needed to perform compliance testing on high-speed serial buses.

• Guides the user through each test setup
• Performs each measurement in accordance with the relevant test procedure
• Compares each measured value with the applicable specification limits
• Fully documents all results
• QualiPHY helps the user perform testing the right way every time!

Real-time Oscilloscope Tests

PHY General Requirements
Test PHY-01 – Unit Interval
Test PHY-02 – Frequency Long-term Accuracy
Test PHY-03 – Spread Spectrum Modulation Frequency
Test PHY-04 – Modulation Deviation

PHY Transmitted Signal Requirements
Test TSG-01 – Differential Output Voltage (all VdiffMin, VdiffMax)
Test TSG-02 – Rise/Fall Times
Test TSG-03 – Differential Skew
Test TSG-04 – AC Common Mode Voltage
Test TSG-05 – Rise/Fall Imbalance
Test TSG-06 – Amplitude Imbalance
Test TSG-09 – Gen1 (1.5 Gb/s) TJ at Connector, fbaud/500
Test TSG-10 – Gen1 (1.5 Gb/s) DJ at Connector, fbaud/500
Test TSG-11 – Gen2 (3.0 Gb/s) TJ at Connector, fbaud/500
Test TSG-12 – Gen2 (3.0 Gb/s) DJ at Connector, fbaud/500
Test TSG-13 – Gen3 Transmit Jitte
Test TSG-14 – Gen3 TX Maximum Differential Voltage
Test TSG-15 – Gen3 TX Minimum Differential Voltage
Test TSG-16 – Gen3 TX AC Common Mode Voltage

PHY OOB Requirements
Test OOB-01 – Signal Detection Threshold
Test OOB-02 – UI During OOB (BitRate)
Test OOB-03 – COMINIT and COMWAKE Burst Length
Test OOB-04 – COMINIT Gap Length
Test OOB-05 – COMWAKE Gap Length
Test OOB-06 – COMWAKE Gap Detection
Test OOB-07 – COMINIT Gap Detection