This article explains the expected behavior of on-die power rails during CMOS switching events, including PDN current flow, clock-edge noise, and asymmetric current draw between switching and latching operations.
Learn how oscilloscope histograms help characterize component specifications by comparing propagation delay, mean, standard deviation, and measurement spread under different conditions.
Anthony is a Program Manager at Teledyne LeCroy’s Austin Labs, and previously a PCIe Product Manager and an FAE. He holds a B.S.E.E. from The University of Texas at San Antonio. Anthony enjoys outdoor activities, especially hiking in the mountains.
PCIe 6.0’s move to PAM4 signaling introduces new compliance pattern measurements—SNDR, RLM, and ps21TX—that require updated test methodologies and noise-aware analysis.
PCIe 6.0 compliance requires SNDR and RLM results with oscilloscope noise removed—these three methods show how to compensate noise accurately in real test setups.
