This article explains how the inductance of passive probe ground leads can dramatically reduce effective bandwidth, distort measurements, and introduce resonance and frequency-response errors.
This tutorial explains a robust oscilloscope-based method for measuring clock jitter using period statistics, track and histogram analysis, and sample-rate verification techniques.
This article introduces the RP2060 and RP4060 power rail probes, designed for modern 48 V power architectures with high offset capability, low-noise measurements, and high-bandwidth power integrity analysis.
Deep dives into high-speed PCI Express signaling, compliance testing, and performance analysis across generations. Covers oscilloscope-based electrical compliance testing and cross-layer (electrical and protocol) analysis for debugging complex problems.
Understanding PCIe’s layered architecture reveals why capturing synchronized physical- and protocol-layer behavior is essential for effective link debugging.
PCIe 6.0’s move to PAM4 signaling introduces new compliance pattern measurements—SNDR, RLM, and ps21TX—that require updated test methodologies and noise-aware analysis.
PCIe 6.0 compliance requires SNDR and RLM results with oscilloscope noise removed—these three methods show how to compensate noise accurately in real test setups.
