This article explains the expected behavior of on-die power rails during CMOS switching events, including PDN current flow, clock-edge noise, and asymmetric current draw between switching and latching operations.
Learn how oscilloscope histograms help characterize component specifications by comparing propagation delay, mean, standard deviation, and measurement spread under different conditions.
Eric is a professor in the EE department at Colorado University, Boulder and a Fellow at Teledyne LeCroy. He has a BS in Physics from MIT and a PhD in Physics from the University of Arizona, Tucson. He enjoys DesignCon and writing for SI Journal.
This article explains the expected behavior of on-die power rails during CMOS switching events, including PDN current flow, clock-edge noise, and asymmetric current draw between switching and latching operations.
Instrumented microcontroller boards and active voltage-rail probes make it possible to directly observe on-die power rail behavior, including sag, noise, and ground bounce.
Dr. Eric Bogatin answers common ground bounce questions covering dI/dt, quiet-low measurements, return path discontinuities, via placement, TDR, and differential probing.
Transmission line losses—driven by skin effect and dielectric properties—play a critical role in degrading high-speed signal integrity and eye performance.
Transmission line loss directly affects eye diagram quality, with around −12 dB at Nyquist marking the limit before signal integrity rapidly degrades without equalization.
