This article explains the expected behavior of on-die power rails during CMOS switching events, including PDN current flow, clock-edge noise, and asymmetric current draw between switching and latching operations.
Learn how oscilloscope histograms help characterize component specifications by comparing propagation delay, mean, standard deviation, and measurement spread under different conditions.
Eric is a professor in the EE department at Colorado University, Boulder and a Fellow at Teledyne LeCroy. He has a BS in Physics from MIT and a PhD in Physics from the University of Arizona, Tucson. He enjoys DesignCon and writing for SI Journal.
Mixed-mode S-parameters are derived from single-ended measurements through matrix transformations that reveal differential and common-mode signal behavior.
This article explains how PDN design, probing method, and measurement location influence power rail noise—and why board-level measurements can be misleading.
This tutorial explains how quiet I/O probing reveals true on-die rail compression—often far greater than what traditional board-level measurements show.
S-parameters reveal how signals reflect and transmit through interconnects, offering powerful insight into impedance, loss, and overall signal integrity.
Accurate power-rail noise measurement requires handling tiny signals on large DC offsets, best achieved with active probes and proper impedance management.
RF pickup can introduce misleading noise into power-rail measurements, but proper shielding and coaxial connections can dramatically reduce interference and reveal true signal behavior.
