This article explains the expected behavior of on-die power rails during CMOS switching events, including PDN current flow, clock-edge noise, and asymmetric current draw between switching and latching operations.
Learn how oscilloscope histograms help characterize component specifications by comparing propagation delay, mean, standard deviation, and measurement spread under different conditions.
Gordon is Director of Product Management for protocol solutions. He has 25 years of experience in PCI/PCI-X/PCIe® technologies, is a PCI-SIG® Chairperson’s Award winner, and contributes test specification and methodologies for PCIe, NVMe® and CXL®.
Understanding PCIe’s layered architecture reveals why capturing synchronized physical- and protocol-layer behavior is essential for effective link debugging.
